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UG473 (v1.11) November 12, 2014
Chapter 3: Built-in Error Correction
ECC Timing Characteristics
The various ECC timing parameters are also shown in Figure 3-4, through Figure 3-7.
Because write clock and read clock are independent of each other, all write timing in
Figure 3-4 is referenced to WRCLK. All read timing in Figure 3-5 is referenced to RDCLK.
Standard ECC Write Timing
Refer to Figure 3-4.
• At time TRCCK_EN, before time T1W, write enable becomes valid at the WREN input
of the block RAM.
• At time TRCCK_ADDR, before time T1W, write address a becomes valid at the
WRADDR[8:0] inputs of the block RAM. WRADDR input is not needed for FIFO.
• At time TRDCK_DI_ECC (standard ECC), before time T1W, write data A (hex)
becomes valid at the DI[63:0] inputs of the block RAM.
• At time TRCKO_ECC_PARITY (standard ECC), after time T1W, ECC parity data PA
(hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.
Standard ECC Read Timing
Refer to Figure 3-5.
• At time TRCCK_EN, before time T1R, read enable becomes valid at the RDEN input
of the block RAM.
• At time TRCCK_ADDR, before time T1R, write address a becomes valid at the
RDADDR[8:0] inputs of the block RAM. RDADDR input is not needed for FIFO.
DO_REG = 0
• At time TRCKO_DO (latch mode), after time T1R, data A (hex) becomes valid at
the DO[63:0] output pins of the block RAM.
• At time TRCKO_DOP (latch mode), after time T1R, data PA (hex) becomes valid
at the DOP[7:0] output pins of the block RAM.
• At time TRCKO_ECC_SBITERR (latch mode), after time T1R, SBITERR is asserted
if single-bit error is detected and corrected on data set A.
• At time TRCKO_ECC_DBITERR (latch mode), after time T2R, DBITERR is
asserted if double-bit error is detected on data set B.
DO_REG = 1
• At time TRCKO_DO (register mode), after time T2R, data A (hex) becomes valid
at the DO[63:0] output pins of the block RAM.
• At time TRCKO_DOP (register mode), after time T2R, data PA (hex) becomes
valid at the DOP[7:0] output pins of the block RAM.
• At time TRCKO_ECCR_SBITERR (register mode), after time T2R, SBITERR is
asserted if single-bit error is detected and corrected on data set A.
• At time TRCKO_ECCR_DBITERR (register mode), after time T3R, DBITERR is
asserted if double-bit error is detected on data set B.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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