RAM 8.0 BUX II Series Guía de usuario Pagina 71

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7 Series FPGAs Memory Resources www.xilinx.com 71
UG473 (v1.11) November 12, 2014
Top-Level View of the Block RAM ECC Architecture
Top-Level View of the Block RAM ECC Architecture
Figure 3-1 shows the top-level view of a 7 series FPGA block RAM in ECC mode.
X-Ref Target - Figure 3-1
Figure 3-1: Top-Level View of Block RAM ECC
wraddr
9
Data In
EN_ECC_WRITE
EN_ECC_READ
EN_ECC_READ
Data
Out
Parity
Out
rdaddr
9
Block RAM
512 x 72
64-bit
ECC
Encode
64
64
64
DI[63:0]
DO[63:0]
0
1
Decode
and
Correct
64
64
RDADDR[8:0]
WRADDR[8:0]
8
DOP[7:0]
RDADDRECC[8:0]
8
ECCPARITY[7:0]
1
INJECTDBITERR
1
INJECTSBITERR
8
8
DIP[7:0]
8
UG473_c3_01_052610
8
0
1
0
1
8
1
0
1
0
1
1
DO_REG
0
1
64
QD
DBITERR
DO_REG
0
1
1
QD
SBITERR
DO_REG
0
1
1
QD
DO_REG
0
1
8
9
QD
DO_REG
0
1
QD
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