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7 Series FPGAs Memory Resources www.xilinx.com 13
UG473 (v1.11) November 12, 2014
Block RAM Introduction
• The A15 pin in the RAMB36E1 should be used for cascading only. In all other cases,
A15 should be left unconnected or tied High.
• An asynchronous assertion or deassertion of the EN signal caused by an
asynchronous reset can violate the setup/hold time of the EN signal. In this case, the
first read or write operation does not yield the expected result. If an asynchronous
assertion or deassertion of EN cannot be avoided, keep EN deasserted during
asynchronous RESET assertion and deassertion or insert a read or write cycle after EN
has been asserted before a valid data cycle occurs. If the PLL or MMCM LOCKED
signal is lost, or a free running clock stops, immediately deassert EN.
Block RAM Introduction
In addition to distributed RAM and high-speed SelectIO™ memory interfaces, 7 series
devices feature a large number of 36 Kb block RAMs. Each 36 Kb block RAM contains two
independently controlled 18 Kb RAMs. Block RAMs are placed in columns, and the total
number of block RAM resources is listed in Table 1-2 by the 7 series device. The 36 Kb
blocks are cascadable to enable a deeper and wider memory implementation, with a
minimal timing penalty.
Table 1-1: Parity Use Scenarios
Primitive
Settings
Effective Read Width Effective Write Width
Read Width Write Width
RAMB18E1 1, 2, or 4 9 or 18 Same as setting 8 or 16
RAMB18E1 9 or 18 1, 2, or 4 8 or 16 Same as setting
RAMB18E1 1, 2, or 4 1, 2, or 4 Same as setting Same as setting
RAMB18E1 9 or 18 9 or 18 Same as setting Same as setting
RAMB36E1 1, 2, or 4 9, 18, or 36 Same as setting 8, 16, or 32
RAMB36E1 9, 18, or 36 1, 2, or 4 8, 16, or 32 Same as setting
RAMB36E1 1, 2, or 4 1, 2, or 4 Same as setting Same as setting
RAMB36E1 9, 18, or 36 9, 18, or 36 Same as setting Same as setting
Notes:
1. Do not use parity bits DIP/DOP when one port width is less than 9 and another port width is 9 or
greater.
Table 1-2: Block RAM Resources in 7 Series Devices
Device
Total 36 Kb Block RAM
Blocks per Device
Number of 36 Kb Block RAM
Columns per Device
Number of 36 Kb Block RAM
Blocks per Column
XC7A15T 25 3 30
(1)(2)(4)
XC7A35T 50 3 30
(1)(2)(4)
XC7A50T 75 3 30
(1)(2)
XC7A75T 105 4 40
(1)(2)(4)
XC7A100T 135 4 40
(1)(2)
XC7A200T 365 9 50
(2)(3)
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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