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UG473 (v1.11) November 12, 2014
Block RAM Port Signals
Register Enable - REGCEA, REGCE, and REGCEB
The register enable pin (REGCE) controls the optional output register. When the RAM is in
register mode, REGCE = 1 registers the output into a register at a clock edge. The polarity
of REGCE is not configurable (active-High). In SDP mode, the REGCEA port is the REGCE.
Set/Reset
RSTREGARSTREG, RSTREGB, RSTRAMARSTRAM, and RSTRAMB
In latch mode, the RSTRAM pin synchronously forces the data output latches to contain
the value SRVAL. See Block RAM Attributes, page 31. When the optional output registers
are enabled (DO_REG = 1), the RSTREG signal synchronously forces the data output
registers contain the SRVAL value. The priority of RSTREG over REGCE is determined
using the RSTREG_PRIORITY attribute. The data output latches or output registers are
synchronously asserted to 0 or 1, including the parity bit. Each port has an independent
SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM memory cells and
does not disturb write operations on the other port. The polarity for both signals is
configurable (active-High by default). In SDP mode, the RSTREGA port is the RSTREG
and the RSTRAMA port is the RSTRAM.
Address Bus - ADDRARDADDR and ADDRBWRADDR
The address bus selects the memory cells for read or write. In SDP mode, the ADDRA port
is the RDADDR and the ADDRB port is the WRADDR. The data bit width of the port
determines the required address bus width for a single RAMB18E1 or RAMB36E1, as
shown in Table 1-9, Table 1-10, Table 1-11, and Table 1-12.
Table 1-9: Port Aspect Ratio for RAMB18E1 (in TDP Mode)
Port Data Width Port Address Width Depth ADDR Bus
DI Bus
DO Bus
DIP Bus
DOP Bus
1 14 16,384 [13:0] [0] NA
2 13 8,192 [13:1] [1:0] NA
4 12 4,096 [13:2] [3:0] NA
9 11 2,048 [13:3] [7:0] [0]
18 10 1,024 [13:4] [15:0] [1:0]
Table 1-10: Port Aspect Ratio for RAMB18E1 (in SDP Mode)
Port Data
Width
(1)
Alternate Port
Width
Port Address
Width
Depth ADDR Bus
DI Bus
DO Bus
DIP Bus
DOP Bus
32 1 14 16,384 [13:0] [0] NA
32 2 13 8,192 [13:1] [1:0] NA
32 4 12 4,096 [13:2] [3:0] NA
36 9 11 2,048 [13:3] [7:0] [0]
36 18 10 1,024 [13:4] [15:0] [1:0]
36 36 9 512 [13:5] [31:0] [3:0]
Notes:
1. Either the Read or Write port is a fixed width of x32 or x36.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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