RAM 8.0 BUX II Series Guía de usuario Pagina 67

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7 Series FPGAs Memory Resources www.xilinx.com 67
UG473 (v1.11) November 12, 2014
Legal Block RAM and FIFO Combinations
Legal Block RAM and FIFO Combinations
The block RAM–FIFO combinations shown in Figure 2-13 are supported in a single
RAMB36 primitive. When placing block RAM and FIFO primitives in the same location,
the FIFO must occupy the lower port.
X-Ref Target - Figure 2-13
Figure 2-13: Legal Block RAM and FIFO Combinations
UG473_c2_13_052610
RAMB18E1
TDP or
SDP Mode
RAMB18E1
TDP or
SDP Mode
RAMB18E1
TDP or
SDP Mode
RAMB18E1
TDP or
SDP Mode
FIFO18E1
FIFO18 Mode
FIFO18E1
FIFO18_36 Mode
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