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7 Series FPGAs Memory Resources www.xilinx.com 47

UG473 (v1.11) November 12, 2014

Synchronous FIFO

Synchronous FIFO Implementations

Table 2-2 outlines varied implementations of synchronous FIFOs. Figure 2-1 shows the

timing differences.

Table 2-2: Comparison of Synchronous FIFO Implementations

Synchronous FIFO Implementations Advantages Disadvantages

EN_SYN = TRUE, DO_REG = 0 No flag uncertainty Longer data output delay (clock-to-out)

EN_SYN = TRUE, DO_REG = 1 Faster data output delay

(clock-to-out), no flag

uncertainty

Data Latency increased by one. Behaves

like a synchronous FIFO with an extra data

output pipeline register

EN_SYN = FALSE, DO_REG = 1

RDCLK = WRCLK

Faster data output delay

(clock-to-out)

Falling-edge flag uncertainty. Rising edge

guaranteed on FULL and EMPTY

X-Ref Target - Figure 2-1

Figure 2-1: Synchronous FIFO Data Timing Diagram

UG473_c2_01_052610

rdclk

rden

EN_SYN = TRUE

DO_REG = 0

EN_SYN = TRUE

DO_REG = 1

EN_SYN = FALSE

DO_REG = 1

CKO_LAT

CKO_REG

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RAM 8.0 BUX II Series Guía de usuario Pagina 47