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UG473 (v1.11) November 12, 2014
Block RAM Applications
Byte-Wide Write Enable
These rules should be considered when using the byte-wide write enable feature:
•For RAMB36E1
• In x72 SDP mode, WEBWE<7:0> is used to connect the eight WE inputs for the
write port. WEA<3:0> is unused.
• In x36 mode, WEA[3:0] is used to connect the four WE inputs for port A and
WEBWE<3:0> is used to connect the four WE inputs for port B. WEBWE<7:4> is
unused.
• In x18 mode, WEA[1:0] is used to connect the two user WE inputs for port A and
WEBWE<1:0> is used to connect the two WE inputs for port B. WEA<3:2> and
WEBWE<7:2> are unused.
• In x9 or smaller port width mode, WEA[0] is used to connect the single user WE
input for port A and WEBWE<0> is used to connect the single WE input for port
B. WEA<3:1> and WEBWE<7:1> are unused.
•For RAMB18E1
• In x36 SDP mode, WEBWE<3:0> is used to connect the four WE inputs for the
write port. WEA<1:0> is unused.
• In x18 mode, WEA[1:0] is used to connect the two WE inputs for port A and
WEBWE<1:0> is used to connect the two WE inputs for port B. WEBWE<3:2> is
unused.
• In x9 or smaller port width mode, WEA[0] is used to connect the single user WE
input for port A and WEBWE<0> is used to connect the single WE input for port
B. WEA<1> and WEBWE<3:1> are unused.
Block RAM Applications
Creating Larger RAM Structures
Block RAM columns have special routing (in addition to the 64K x 1 cascade) to create
wider/deeper blocks using 36 Kb block RAMs with minimal routing delays. Wider or
deeper RAM structures are achieved with a smaller timing penalty than is encountered
when using normal routing resources.
Synthesis inference or the Xilinx CORE Generator tool program offers you an easy way to
generate wider and deeper memory structures using multiple block RAM instances. This
program outputs VHDL or Verilog instantiation templates and simulation models, along
with an EDIF file for inclusion in a design.
Block RAM RSTREG in Register Mode
A block RAM RSTREG in register mode can be used to control the output register as a true
pipeline register independent of the block RAM. As shown in Figure 1-11, block RAM can
be read and written independent of register enable or set/reset. In register mode RSTREG
sets DO to the SRVAL and data can be read from the block RAM to DBRAM. Data at
DBRAM can be clocked out (DO) on the next cycle. The timing diagrams in Figure 1-12
through Figure 1-14 show different cases of the RSTREG operation.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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