RAM 8.0 BUX II Series Guía de usuario Pagina 79

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7 Series FPGAs Memory Resources www.xilinx.com 79
UG473 (v1.11) November 12, 2014
ECC Modes of Operation
Note relevant to Figure 3-8:
1. Data (DOUT) and corresponding address (ECCRDADDR) are available to you in same
phase.
Note relevant to Figure 3-9:
1. Data (DOUT) and corresponding address (ECCRDADDR) are available to you in same
phase.
Standard ECC
Set by Attributes
EN_ECC_READ = TRUE
EN_ECC_WRITE = TRUE
X-Ref Target - Figure 3-8
Figure 3-8: ECCRDADDR Timing in Register Mode
RDADDR
RDCLK
RDEN/REGCE
DOUT
SBITERR
DBITERR
1
2
3
4
ABxC D
UG473_c3_08_052610
ECCRDADDR
5
6
1
2 3 4
5
E
SBITERR Corrected Data DBITERR Not Corrected Data
X-Ref Target - Figure 3-9
Figure 3-9: ECCRDADDR Timing in Latch Mode
RDADDR
RDCLK
RDEN/REGCE
DOUT
SBITERR
DBITERR
1
2
3
4
ABxC D
UG473_c3_09_052610
ECCRDADDR
5
6
1
2 3 4
5
E
SBITERR Corrected Data DBITERR Not Corrected Data
6
F
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