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7 Series FPGAs Memory Resources www.xilinx.com 51

UG473 (v1.11) November 12, 2014

FIFO Operations

Reset

A reset synchronizer circuit has been introduced to 7 series FPGAs. RST must be asserted

for five cycles to reset all read and write address counters and initialize flags after

power-up. RST does not clear the memory, nor does it clear the output register. When RST

is asserted High, EMPTY and ALMOSTEMPTY are set to 1, FULL and ALMOSTFULL are

reset to 0. The RST signal must be High for at least five read clock and write clock cycles to

ensure all internal states are reset to correct values. During Reset, both RDEN and WREN

must be deasserted (held Low).

Operating Mode

There are two operating modes in FIFO functions. They differ only in output behavior

immediately after the first word is written to a previously empty FIFO.

Standard Mode

After the first word is written into an empty FIFO, the Empty flag is deasserted

synchronously with RDCLK. After Empty is deasserted Low and RDEN is asserted, the

first word appears at DO on the rising edge of RDCLK.

First Word Fall Through (FWFT) Mode

After the first word is written into an empty FIFO, this word automatically appears at DO

before RDEN is asserted. Subsequent Read operations require Empty to be Low and RDEN

to be High. Figure 2-5 illustrates the difference between standard mode and FWFT mode.

Status Flags

Table 2-4 shows the number of clock cycles to assert or deassert each flag of a dual-clock

FIFO. Synchronous FIFOs do not have a clock cycle latency when asserting or deasserting

flags. Due to the asynchronous nature of the clocks, the simulation model only reflects the

deassertion latency cycles listed.

X-Ref Target - Figure 2-5

Figure 2-5: Read Cycle Timing (Standard and FWFT Modes)

RDCLK

RDEN

EMPTY

DO (Standard)

DO (FWFT)

Previous Data

W2 W3

UG473_c2_05_052610

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RAM 8.0 BUX II Series Guía de usuario Pagina 51