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54 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 2: Built-in FIFO Support
Table 2-6 shows how the SRVAL and INIT bit locations map to the DO outputs for the FIFO
primitives.
FIFO_MODE String FIFO36,
FIFO36_72
FIFO36 Selects the FIFO36 modes.
FIFO18,
FIFO18_36
FIFO18 Selects the FIFO18 modes.
EN_SYN Boolean FALSE,
TRUE
FALSE When set to TRUE, ties WRCLK and
RDCLK together.
When set to TRUE, FWFT must be
FALSE.
When set to FALSE, DO_REG must be 1.
SRVAL
(1)
Hex Any 36-bit value
in FIFO18E1 and
any 72-bit value
in FIFO36E1
00h Controls the value of the FIFO output
when RSTREG is asserted. Only
supported when DO_REG = 1 and
EN_SYN = TRUE and RSTREG is
connected to an active signal.
INIT
(1)
Hex Any 36-bit value
in FIFO18E1 and
any 72-bit value
in FIFO36E1
00h Specifies the initial value on the output
after configuration, when DO_REG = 1
and EN_SYN = TRUE.
Notes:
1. Table 2-6 shows how the SRVAL and INIT bit locations map to the DO outputs for the FIFO primitives.
Table 2-5: FIFO18E1 and FIFO36E1 Attributes (Cont’d)
Attribute Name Type Values Default Notes
Table 2-6: FIFO18E1/FIFO36E1 SRVAL/INIT Mapping
Port Width SRVAL/INIT
SRVAL/INIT Mapping to DO SRVAL/INIT Mapping to DOP
DO SRVAL/INIT DOP SRVAL/INIT
4 [3:0] [3:0] [3:0] NA NA
9 [8:0] [7:0] [7:0] [0] [8]
18 [17:0] [15:0] [15:0] [1:0] [17:16]
36 (for FIFO36E1) [35:0] [31:0] [31:0] [3:0] [35:32]
36 (for FIFO18_36) [35:0] [31:0] [33:18],[15:0] [3:0] [35:34],[17:16]
72 (for FIFO36_72) [71:0] [63:0] [67:36],[31:0] [7:0] [71:68],[35:32]
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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