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UG473 (v1.11) November 12, 2014
Chapter 1: Block RAM Resources
Content Initialization - INITP_xx
INITP_xx attributes define the initial contents of the memory cells corresponding to
DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros.
The initialization attributes represent the memory contents of the parity bits. The eight
initialization attributes are INITP_00 through INITP_07 for the RAMB18E1. The
16 initialization attributes are INITP_00 through INITP_0F for the RAMB36E1. Each
INITP_xx is a 64-digit hex-encoded bit vector with a regular INIT_xx attribute behavior.
The same formula can be used to calculate the bit positions initialized by a particular
INITP_xx attribute.
Output Latches Initialization - INIT (INIT_A or INIT_B)
The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output
latches or output register values after configuration. The width of the INIT (INIT_A and
INIT_B) attribute is the port width, as shown in Table 1-16. These attributes are
hex-encoded bit vectors, and the default value is 0. In cascade mode, both the upper and
lower block RAM should be initialized to the same value.
Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B])
The SRVAL (single-port) or SRVAL_A and SRVAL_B (dual-port) attributes define output
latch values when the RSTRAM/RSTREG input is asserted. The width of the SRVAL
(SRVAL_A and SRVAL_B) attribute is the port width, as shown in Table 1-16. These
attributes are hex-encoded bit vectors and the default value is 0. This attribute sets the
value of the output register when the optional output register attribute is set. When the
register is not used, the latch gets set to the SRVAL instead. Table 1-16 and Table 1-17 show
how the SRVAL and INIT bit locations map to the DO outputs for the block RAM
primitives and the SDP macro.
…… …
INIT_2F 12287 12032
INIT_30 12543 12288
…… …
INIT_3F 16383 16128
…… …
INIT_7F 32767 32512
Table 1-15: Block RAM Initialization Attributes (Cont’d)
Attribute
Memory Location
From To
Table 1-16: RAMB18E1 and RAMB36E1, SRVAL and INIT Mapping for Port A and Port B
Port Width
SRVAL/INIT_(A/B)
Full Width
SRVAL/INIT_(A/B) Mapping to DO SRVAL/INIT_(A/B) Mapping to DOP
DOADO/DOBDO (SRVAL/INIT)_(A/B) DOP(A/B)/DOP SRVAL/INIT_(A/B)
1 [0] [0] [0] N/A N/A
2 [1:0] [1:0] [1:0] N/A N/A
4 [3:0] [3:0] [3:0] N/A N/A
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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