RAM 7.0 Guía de usuario

DS512 March 1, 2011 www.xilinx.com 1Product Specification© 2006–2011 Xilinx, Inc. XILINX, the Xilinx logo, Kintex, Virtex, Spartan, ISE and other desi

LogiCORE IP Block Memory Generator v6.110 www.xilinx.com DS512 March 1, 2011Product SpecificationFigure 9 illustrates single burst Read operations to

LogiCORE IP Block Memory Generator v6.1100 www.xilinx.com DS512 March 1, 2011Product SpecificationVirtex-5 FPGA: Memory with Primitive Output Register

DS512 March 1, 2011 www.xilinx.com 101Product SpecificationLogiCORE IP Block Memory Generator v6.1Virtex-4 FPGA: Memory with Primitive Output Register

LogiCORE IP Block Memory Generator v6.1102 www.xilinx.com DS512 March 1, 2011Product SpecificationVirtex-4 FPGA: Memory with Primitive Output Register

DS512 March 1, 2011 www.xilinx.com 103Product SpecificationLogiCORE IP Block Memory Generator v6.1Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4

LogiCORE IP Block Memory Generator v6.1104 www.xilinx.com DS512 March 1, 2011Product SpecificationKintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4

DS512 March 1, 2011 www.xilinx.com 105Product SpecificationLogiCORE IP Block Memory Generator v6.1Spartan-6 or Spartan-3A DSP FPGA: Output Register Co

LogiCORE IP Block Memory Generator v6.1106 www.xilinx.com DS512 March 1, 2011Product SpecificationSpartan-6 or Spartan-3A DSP FPGA: Memory with Primit

DS512 March 1, 2011 www.xilinx.com 107Product SpecificationLogiCORE IP Block Memory Generator v6.1Spartan-6 or Spartan-3A DSP FPGA: Memory With Primit

LogiCORE IP Block Memory Generator v6.1108 www.xilinx.com DS512 March 1, 2011Product SpecificationSpartan-6 or Spartan-3A DSP FPGA: Memory with Primit

DS512 March 1, 2011 www.xilinx.com 109Product SpecificationLogiCORE IP Block Memory Generator v6.1Spartan-6 or Spartan-3A DSP FPGA: Memory with Primit

DS512 March 1, 2011 www.xilinx.com 11Product SpecificationLogiCORE IP Block Memory Generator v6.1In compliance with AXI Protocol, the burst terminatio

LogiCORE IP Block Memory Generator v6.1110 www.xilinx.com DS512 March 1, 2011Product SpecificationPort A or Port B Register Port A Output of Memory P

DS512 March 1, 2011 www.xilinx.com 111Product SpecificationLogiCORE IP Block Memory Generator v6.1Spartan-6 or Spartan-3A DSP FPGA: Memory with Core O

LogiCORE IP Block Memory Generator v6.1112 www.xilinx.com DS512 March 1, 2011Product SpecificationSpartan-6 or Spartan-3A DSP FPGA: Memory with No Out

DS512 March 1, 2011 www.xilinx.com 113Product SpecificationLogiCORE IP Block Memory Generator v6.1Spartan-3 FPGA: Memory with Primitive and Core Outpu

LogiCORE IP Block Memory Generator v6.1114 www.xilinx.com DS512 March 1, 2011Product SpecificationSpartan-3 FPGA: Memory with Primitive Output Registe

DS512 March 1, 2011 www.xilinx.com 115Product SpecificationLogiCORE IP Block Memory Generator v6.1Spartan-3 FPGA: Memory with Core Output RegistersFig

LogiCORE IP Block Memory Generator v6.1116 www.xilinx.com DS512 March 1, 2011Product SpecificationSpartan-3 FPGA: Memory with No Output RegistersWhen

DS512 March 1, 2011 www.xilinx.com 117Product SpecificationLogiCORE IP Block Memory Generator v6.1Support Xilinx provides technical support for this L

LogiCORE IP Block Memory Generator v6.1118 www.xilinx.com DS512 March 1, 2011Product SpecificationNotice of DisclaimerXilinx is providing this product

LogiCORE IP Block Memory Generator v6.112 www.xilinx.com DS512 March 1, 2011Product Specificationaccepting the Read burst data (by negating RREADY), t

DS512 March 1, 2011 www.xilinx.com 13Product SpecificationLogiCORE IP Block Memory Generator v6.1RAM will see the following sequence of addresses for

LogiCORE IP Block Memory Generator v6.114 www.xilinx.com DS512 March 1, 2011Product SpecificationFigure 14 illustrates the timing on AXI WRAP or cache

DS512 March 1, 2011 www.xilinx.com 15Product SpecificationLogiCORE IP Block Memory Generator v6.1AXI4 Narrow TransactionsA narrow burst is defined as

LogiCORE IP Block Memory Generator v6.116 www.xilinx.com DS512 March 1, 2011Product SpecificationFigure 16 illustrates an example of AXI “narrow” Read

DS512 March 1, 2011 www.xilinx.com 17Product SpecificationLogiCORE IP Block Memory Generator v6.1something other than 0x0h, 0x4h, 0x8h, etc. The examp

LogiCORE IP Block Memory Generator v6.118 www.xilinx.com DS512 March 1, 2011Product Specificationaddressing. Table 5 illustrates some example setting

DS512 March 1, 2011 www.xilinx.com 19Product SpecificationLogiCORE IP Block Memory Generator v6.1Optional Pipeline Stages Pipeline stages are currentl

LogiCORE IP Block Memory Generator v6.12 www.xilinx.com DS512 March 1, 2011Product SpecificationFeaturesFeatures Common to the Native Interface and AX

LogiCORE IP Block Memory Generator v6.120 www.xilinx.com DS512 March 1, 2011Product SpecificationThe Dual-port ROM allows Read access to the memory sp

DS512 March 1, 2011 www.xilinx.com 21Product SpecificationLogiCORE IP Block Memory Generator v6.1Note: For Virtex family architectures, Read access is

LogiCORE IP Block Memory Generator v6.122 www.xilinx.com DS512 March 1, 2011Product SpecificationSelectable Memory AlgorithmThe Block Memory Generator

DS512 March 1, 2011 www.xilinx.com 23Product SpecificationLogiCORE IP Block Memory Generator v6.1multiplexers than the minimum area algorithm. Figure

LogiCORE IP Block Memory Generator v6.124 www.xilinx.com DS512 March 1, 2011Product Specificationmemory structures to enhance performance. Table 6 sho

DS512 March 1, 2011 www.xilinx.com 25Product SpecificationLogiCORE IP Block Memory Generator v6.1When using data-width aspect ratios, the primitive ty

LogiCORE IP Block Memory Generator v6.126 www.xilinx.com DS512 March 1, 2011Product SpecificationThe operating modes have an effect on the relationshi

DS512 March 1, 2011 www.xilinx.com 27Product SpecificationLogiCORE IP Block Memory Generator v6.1• No Change Mode: In NO_CHANGE mode, the output latch

LogiCORE IP Block Memory Generator v6.128 www.xilinx.com DS512 March 1, 2011Product SpecificationKintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 R

DS512 March 1, 2011 www.xilinx.com 29Product SpecificationLogiCORE IP Block Memory Generator v6.1BW0 is made up of AW3, AW2, AW1, and AW0. In the same

DS512 March 1, 2011 www.xilinx.com 3Product SpecificationLogiCORE IP Block Memory Generator v6.1• Supports data widths from up to 256 bits and memory

LogiCORE IP Block Memory Generator v6.130 www.xilinx.com DS512 March 1, 2011Product SpecificationByte-Write ExampleConsider a Single-port RAM with a d

DS512 March 1, 2011 www.xilinx.com 31Product SpecificationLogiCORE IP Block Memory Generator v6.1• Using Byte-Writes. When using byte-writes, memory c

LogiCORE IP Block Memory Generator v6.132 www.xilinx.com DS512 March 1, 2011Product Specificationdefine the Write-to-Read relationship of the A or B p

DS512 March 1, 2011 www.xilinx.com 33Product SpecificationLogiCORE IP Block Memory Generator v6.1Figure 34 shows a memory configuration with registers

LogiCORE IP Block Memory Generator v6.134 www.xilinx.com DS512 March 1, 2011Product SpecificationFor Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4,

DS512 March 1, 2011 www.xilinx.com 35Product SpecificationLogiCORE IP Block Memory Generator v6.1The pipeline stages are common for port A and port B

LogiCORE IP Block Memory Generator v6.136 www.xilinx.com DS512 March 1, 2011Product SpecificationOptional Register Clock Enable PinsThe optional outpu

DS512 March 1, 2011 www.xilinx.com 37Product SpecificationLogiCORE IP Block Memory Generator v6.1Optional Set/Reset PinsThe set/reset pins (RSTA and R

LogiCORE IP Block Memory Generator v6.138 www.xilinx.com DS512 March 1, 2011Product SpecificationFigure 38 depicts how REGCE can be used to latch the

DS512 March 1, 2011 www.xilinx.com 39Product SpecificationLogiCORE IP Block Memory Generator v6.1Figure 40 illustrates the reset behavior when the Res

LogiCORE IP Block Memory Generator v6.14 www.xilinx.com DS512 March 1, 2011Product SpecificationMemory TypesThe Block Memory Generator core uses embed

LogiCORE IP Block Memory Generator v6.140 www.xilinx.com DS512 March 1, 2011Product SpecificationThe special reset behavior of Spartan-3A DSP devices

DS512 March 1, 2011 www.xilinx.com 41Product SpecificationLogiCORE IP Block Memory Generator v6.1does not appear at the output. At the time of the thi

LogiCORE IP Block Memory Generator v6.142 www.xilinx.com DS512 March 1, 2011Product Specification• Reset Type: This option determines if the reset is

DS512 March 1, 2011 www.xilinx.com 43Product SpecificationLogiCORE IP Block Memory Generator v6.111 1“CE”, “SR”“SYNC”, “ASYNC”Both memory latch and em

LogiCORE IP Block Memory Generator v6.144 www.xilinx.com DS512 March 1, 2011Product SpecificationBuilt-in Error Correction Capability and Error Inject

DS512 March 1, 2011 www.xilinx.com 45Product SpecificationLogiCORE IP Block Memory Generator v6.1Figure 46 illustrates a typical Write and Read operat

LogiCORE IP Block Memory Generator v6.146 www.xilinx.com DS512 March 1, 2011Product SpecificationFigure 47 shows the assertion of the SBITERR and DBIT

DS512 March 1, 2011 www.xilinx.com 47Product SpecificationLogiCORE IP Block Memory Generator v6.1• Single-bit errors are corrected• Double-bit errors

LogiCORE IP Block Memory Generator v6.148 www.xilinx.com DS512 March 1, 2011Product Specification.Figure 48 illustrates the implementation of Soft ECC

DS512 March 1, 2011 www.xilinx.com 49Product SpecificationLogiCORE IP Block Memory Generator v6.1Parameters • softecc: This parameter enables the Soft

DS512 March 1, 2011 www.xilinx.com 5Product SpecificationLogiCORE IP Block Memory Generator v6.1• In Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex

LogiCORE IP Block Memory Generator v6.150 www.xilinx.com DS512 March 1, 2011Product Specification• When the use_error_injection_pins parameter is enab

DS512 March 1, 2011 www.xilinx.com 51Product SpecificationLogiCORE IP Block Memory Generator v6.1X-Ref Target - Figure 50Figure 50: GUI Page 3: Enabli

LogiCORE IP Block Memory Generator v6.152 www.xilinx.com DS512 March 1, 2011Product SpecificationTiming DiagramsFigure 51 illustrates a typical Write

DS512 March 1, 2011 www.xilinx.com 53Product SpecificationLogiCORE IP Block Memory Generator v6.1Figure 52 shows the assertion of the SBITERR and DBIT

LogiCORE IP Block Memory Generator v6.154 www.xilinx.com DS512 March 1, 2011Product SpecificationDevice Utilization and Performance Benchmarks Smaller

DS512 March 1, 2011 www.xilinx.com 55Product SpecificationLogiCORE IP Block Memory Generator v6.1Lower Data Widths in Kintex-7, Virtex-7, and Virtex-6

LogiCORE IP Block Memory Generator v6.156 www.xilinx.com DS512 March 1, 2011Product Specificationsimulation models generated. Table 15 defines the dif

DS512 March 1, 2011 www.xilinx.com 57Product SpecificationLogiCORE IP Block Memory Generator v6.1AXI4 Interface Block Memory Generator Signal ListAXI4

LogiCORE IP Block Memory Generator v6.158 www.xilinx.com DS512 March 1, 2011Product SpecificationS_AXI_AWLEN[7:0] InputBurst Length. The burst length

DS512 March 1, 2011 www.xilinx.com 59Product SpecificationLogiCORE IP Block Memory Generator v6.1S_AXI_BRESP[1:0] OutputWrite Response. This signal in

LogiCORE IP Block Memory Generator v6.16 www.xilinx.com DS512 March 1, 2011Product SpecificationAXI4 Interface Block Memory Generator Feature SummaryO

LogiCORE IP Block Memory Generator v6.160 www.xilinx.com DS512 March 1, 2011Product SpecificationAXI4-Lite Interface SignalsAXI4 Read Data Channel Int

DS512 March 1, 2011 www.xilinx.com 61Product SpecificationLogiCORE IP Block Memory Generator v6.1AXI4-Lite Write Data Channel Interface SignalsS_AXI_W

LogiCORE IP Block Memory Generator v6.162 www.xilinx.com DS512 March 1, 2011Product SpecificationGenerating the Block Memory Generator CoreGenerating

DS512 March 1, 2011 www.xilinx.com 63Product SpecificationLogiCORE IP Block Memory Generator v6.1• Native Block Memory Generator First Screen• Port Op

LogiCORE IP Block Memory Generator v6.164 www.xilinx.com DS512 March 1, 2011Product Specification• AXI4: Implements an AXI4 Interface Block Memory Gen

DS512 March 1, 2011 www.xilinx.com 65Product SpecificationLogiCORE IP Block Memory Generator v6.1• Built-In ECC. When targeting Kintex-7, Virtex-7, Vi

LogiCORE IP Block Memory Generator v6.166 www.xilinx.com DS512 March 1, 2011Product SpecificationWrite EnableWhen targeting Kintex-7, Virtex-7, Virtex

DS512 March 1, 2011 www.xilinx.com 67Product SpecificationLogiCORE IP Block Memory Generator v6.1•NO_CHANGE•EnableSelect the enable type:• Always enab

LogiCORE IP Block Memory Generator v6.168 www.xilinx.com DS512 March 1, 2011Product SpecificationOutput Registers and Memory Initialization ScreenOpti

DS512 March 1, 2011 www.xilinx.com 69Product SpecificationLogiCORE IP Block Memory Generator v6.1The MUX size displayed in the GUI can be used to dete

DS512 March 1, 2011 www.xilinx.com 7Product SpecificationLogiCORE IP Block Memory Generator v6.1All Write operations are initiated on the Write Addres

LogiCORE IP Block Memory Generator v6.170 www.xilinx.com DS512 March 1, 2011Product Specification• Output Reset Value (Hex): Specify the reset value o

DS512 March 1, 2011 www.xilinx.com 71Product SpecificationLogiCORE IP Block Memory Generator v6.1Simulation Model Options and Information ScreenX-Ref

LogiCORE IP Block Memory Generator v6.172 www.xilinx.com DS512 March 1, 2011Product SpecificationPower Estimate OptionsThe Power Estimation tab on the

DS512 March 1, 2011 www.xilinx.com 73Product SpecificationLogiCORE IP Block Memory Generator v6.1Behavioral Simulation Model OptionsSelect the type of

LogiCORE IP Block Memory Generator v6.174 www.xilinx.com DS512 March 1, 2011Product Specification• If the memory width is an integral multiple of the

DS512 March 1, 2011 www.xilinx.com 75Product SpecificationLogiCORE IP Block Memory Generator v6.1Interface Type Selection ScreenThe main Block Memory

LogiCORE IP Block Memory Generator v6.176 www.xilinx.com DS512 March 1, 2011Product SpecificationAXI4 Interface OptionsAXI4 Interface Options• AXI4: I

DS512 March 1, 2011 www.xilinx.com 77Product SpecificationLogiCORE IP Block Memory Generator v6.1Block Memory Generator Resource Utilization and Perfo

LogiCORE IP Block Memory Generator v6.178 www.xilinx.com DS512 March 1, 2011Product SpecificationOutput RegistersThe Block Memory Generator optional o

DS512 March 1, 2011 www.xilinx.com 79Product SpecificationLogiCORE IP Block Memory Generator v6.1In Virtex-6, Virtex-5, Virtex-4, and Spartan-6 archit

LogiCORE IP Block Memory Generator v6.18 www.xilinx.com DS512 March 1, 2011Product SpecificationFigure 4 shows an example application for AXI4-Lite Me

LogiCORE IP Block Memory Generator v6.180 www.xilinx.com DS512 March 1, 2011Product SpecificationAspect RatiosThe Block Memory Generator selectable po

DS512 March 1, 2011 www.xilinx.com 81Product SpecificationLogiCORE IP Block Memory Generator v6.1AlgorithmThe differences between the minimum area, lo

LogiCORE IP Block Memory Generator v6.182 www.xilinx.com DS512 March 1, 2011Product SpecificationTable 35 shows examples of the resource utilization a

DS512 March 1, 2011 www.xilinx.com 83Product SpecificationLogiCORE IP Block Memory Generator v6.1AXI4 Block Memory Generator Resource Utilization and

LogiCORE IP Block Memory Generator v6.184 www.xilinx.com DS512 March 1, 2011Product SpecificationNative Block Memory Generator Supplemental Informatio

DS512 March 1, 2011 www.xilinx.com 85Product SpecificationLogiCORE IP Block Memory Generator v6.1www.xilinx.com/products/design_resources/power_centra

LogiCORE IP Block Memory Generator v6.186 www.xilinx.com DS512 March 1, 2011Product Specification• The Low Power algorithm disables the “Always Enable

DS512 March 1, 2011 www.xilinx.com 87Product SpecificationLogiCORE IP Block Memory Generator v6.1should contain 256 32-bit wide entries. The first 128

LogiCORE IP Block Memory Generator v6.188 www.xilinx.com DS512 March 1, 2011Product Specification4 C_MEM_TYPE Integer0: Single Port RAM1: Simple Dual

DS512 March 1, 2011 www.xilinx.com 89Product SpecificationLogiCORE IP Block Memory Generator v6.118C_HAS_MUX_OUTPUT_REGS_A Integer 0,1 Determines whet

DS512 March 1, 2011 www.xilinx.com 9Product SpecificationLogiCORE IP Block Memory Generator v6.1Supported Devices AXI4 BMG Core Channel Handshake Sequ

LogiCORE IP Block Memory Generator v6.190 www.xilinx.com DS512 March 1, 2011Product Specification42 C_INITB_VAL String “…”Defines initialization/power

DS512 March 1, 2011 www.xilinx.com 91Product SpecificationLogiCORE IP Block Memory Generator v6.1AXI4 Interface Block Memory Generator SIM Parameters5

LogiCORE IP Block Memory Generator v6.192 www.xilinx.com DS512 March 1, 2011Product Specification4 C_INTERFACE_TYPE Integer0: Native 1: AXI4Determine

DS512 March 1, 2011 www.xilinx.com 93Product SpecificationLogiCORE IP Block Memory Generator v6.120 C_HAS_MEM_OUTPUT_REGS_A Integer 0Determines whethe

LogiCORE IP Block Memory Generator v6.194 www.xilinx.com DS512 March 1, 2011Product Specification44 C_HAS_REGCEB Integer 0Determines whether port B

DS512 March 1, 2011 www.xilinx.com 95Product SpecificationLogiCORE IP Block Memory Generator v6.154 C_RSTRAM_B Integer 0Applicable for Kintex-7, Virte

LogiCORE IP Block Memory Generator v6.196 www.xilinx.com DS512 March 1, 2011Product SpecificationOutput Register ConfigurationsThe Block Memory Genera

DS512 March 1, 2011 www.xilinx.com 97Product SpecificationLogiCORE IP Block Memory Generator v6.1For Kintex-7, Virtex-7, and Virtex-6, when only Regis

LogiCORE IP Block Memory Generator v6.198 www.xilinx.com DS512 March 1, 2011Product SpecificationKintex-7, Virtex-7, and Virtex-6 FPGAs: Memory with P

DS512 March 1, 2011 www.xilinx.com 99Product SpecificationLogiCORE IP Block Memory Generator v6.1Kintex-7, Virtex-7, and Virtex-6 FPGAs: Memory with P