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UG473 (v1.11) November 12, 2014
Block RAM and FIFO ECC Port Descriptions
Table 3-2 lists and describes the FIFO ECC I/O port names.
Table 3-2: FIFO ECC Port Names and Descriptions
Port Name Direction Signal Description
DI[63:0] Input Data input bus.
DIP[7:0] Input Data input parity bus. Not used when standard mode is used.
WREN Input Write enable. When WREN = 1, data is written into memory. When WREN = 0, write
is disabled.
RDEN Input Read enable. When RDEN = 1, data is read from memory. When RDEN = 0, read is
disabled.
RSTREG Input Not supported when using the block RAM ECC primitive. Always connect to GND.
RSTRAM Input Not supported when using the block RAM ECC primitive. Always connect to GND.
RST Input Asynchronous reset of FIFO counter and flags. Reset must be asserted for three clock
cycles. Reset does not affect DO or ECC signals.
WRCLK Input Clock for write operations.
RDCLK Input Clock for read operations.
INJECTSBITERR Input Creates a single-bit error at a particular block RAM bit when asserted during write.
The block RAM ECC logic corrects this error when this location is read back. The error
is created in bit DI[30].
INJECTDBITERR Input Creates a double-bit error at two particular block RAM bits when asserted during
write. The block RAM ECC logic flags a double-bit error when this location is read
back. When both INJECTBITERR signals are simultaneously asserted, a double-bit
error is injected. The errors are created in bit DI[30] and DI[62].
DO[63:0] Output Data output bus.
DOP[7:0] Output Data output parity bus.
SBITERR
(1)
Output Single-bit error status.
DBITERR
(1)
Output Double-bit error status.
ECCPARITY[7:0] Output Not supported.
FULL Output FIFO Full flag.
ALMOSTFULL Output FIFO Almost Full flag.
EMPTY Output FIFO Empty flag.
ALMOSTEMPTY Output FIFO Almost Empty flag.
RDCOUNT Output The FIFO data read pointer.
WRCOUNT Output The FIFO data write pointer.
WRERR Output When the FIFO is full, any additional write operation generates an error flag.
RDERR Output When the FIFO is empty, any additional read operation generates an error flag.
Notes:
1. Hamming code implemented in the FIFO ECC logic detects one of three conditions: no detectable error, single-bit error detected and
corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and DBITERR
indicate these three conditions.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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