RAM 8.0 BUX II Series Guía de usuario Pagina 38

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38 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 1: Block RAM Resources
X-Ref Target - Figure 1-11
Figure 1-11: Block RAM RSTREG in Register Mode
X-Ref Target - Figure 1-12
Figure 1-12: Block RAM Reset Operation in RSTREG Mode
X-Ref Target - Figure 1-13
Figure 1-13: Block RAM Reset Operation in REGCE Mode
Block RAM
Output
Register
RSTRAM
DO
RAMENEN
REGCE
RSTREG
RSTRAM
DI
DBRAM
UG473_c1_11_040411
DBRAM
CLK REGCLK
RAMEN
REGCE
RSTRAM
RSTREG
DO
D0 SRVAL(1REG) D1 SRVAL(2REG) SRVAL(1LAT)
D1 D3D0
SRVAL(1LAT)
UG473_c1_12_040411
DBRAM
CLK REGCLK
RAMEN
REGCE
RSTRAM
RSTREG
DO
D0 SRVAL(1REG) D1 SRVAL(1LAT)
D1 D3D0
SRVAL(1LAT)
UG473_c1_13_040411
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