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UG473 (v1.11) November 12, 2014

Block RAM Initialization in VHDL or Verilog Code

The RAMB36_X0Y0 is the bottom-left block RAM location on the device. If RAMB36E1 is

constrained to RAMB36_X#Y#, the FIFO cannot be constrained to FIFO36_X#Y# because

they share a location.

Two RAMB18E1s can be placed in the same RAMB36E1 location:

inst ”my_ramb18_2” LOC = RAMB36_X0Y0

inst ”my_ramb18_1” LOC = RAMB36_X0Y0

In addition, one FIFO18 and one RAMB18 can be placed in the same RAMB36E1 location:

inst “my_ramb18” LOC = RAMB36_X0Y0

inst ”my_fifo18” LOC = RAMB36_X0Y0

Block RAM Initialization in VHDL or Verilog Code

Block RAM attributes and content can be initialized in VHDL or Verilog code for both

synthesis and simulation by using generic maps (VHDL) or defparams (Verilog) within the

instantiated component. Modifying the values of the generic map or defparam affects both

the simulation behavior and the implemented synthesis results. Inferred block RAM can be

initialized as well. The 7 Series FPGAs Libraries Guide includes the code to instantiate the

RAMB36E1 primitive.

Additional RAMB18E1 and RAMB36E1 Primitive Design

Considerations

The RAMB18E1 and RAMB36E1 primitives are integral in the 7 series FPGAs block RAM

solution.

Optional Output Registers

Optional output registers can be used at either or both A|B output ports of RAMB18E1

and RAMB36E1. The choice is made using the DO[A|B]_REG attribute. The two

independent clock enable pins are REGCE[A|B]. When using the optional output registers

at port [A|B], assertion of the synchronous set/reset (RSTREG and RSTRAM) pins of ports

[A|B] causes the value specified by the attribute SRVAL to be registered at the output.

Figure 1-5 shows an optional output register.

Independent Read and Write Port Width

To specify the port widths using the dual-port mode of the block RAM, designers must use

the READ_WIDTH_[A|B] and WRITE_WIDTH_[A|B] attributes. These rules should be

considered:

• Designing a single port block RAM requires the port pair widths of one write and one

read to be set (for example, READ_WIDTH_A and WRITE_WIDTH_A).

• Designing a dual-port block RAM requires all port widths to be set.

• When using these attributes, if both write ports or both read ports are set to 0, the

Xilinx ISE® tools do not implement the design. In simple dual-port mode, one side of

the ports is fixed while the other side can have a variable width. The RAMB18E1 has a

data port width of up to 36, while the RAMB36E1 has a data port width of up to 72.

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