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46 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 2: Built-in FIFO Support
Two operating modes affect the reading of the first word after the FIFO is emptied:
• In standard mode, the first word written into an empty FIFO appears at DO after you
have activated RDEN. You must pull the data out of the FIFO.
• In FWFT mode, the first word written into an empty FIFO automatically appears at
DO without you activating RDEN. The next RDEN then pulls the subsequent data
word onto DO.
• Standard and FWFT mode differ only in the reading of the first word entry after the
FIFO is empty.
The EN_SYN = FALSE setting is used in these cases:
• when the clocks are asynchronous
• when the frequencies of the two clocks are the same but the phase is different
• when one frequency is a multiple of the other.
Synchronous FIFO
When using 7 series FPGAs synchronous FIFOs, set the EN_SYN attribute to TRUE to
eliminate clock cycle latency when asserting or deasserting flags.
When the built-in FIFO is used as a synchronous FIFO with the EN_SYN attribute set to
TRUE and the reset is asynchronous, the behavior of the flags is not predictable after the
first write. In this case, Xilinx recommends synchronizing the reset or synchronizing only
the negative edge of reset to the RDCLK or WRCLK. This synchronization is not required
in configurations where EN_SYN is set to FALSE.
First-word fall-through (FWFT) mode is only supported in the dual-clock FIFO
(EN_SYN = FALSE). Table 2-1 shows the FIFO capacity in the two modes.
Table 2-1: FIFO Capacity
Standard Mode FWFT Mode
18 Kb FIFO 36 Kb FIFO 18 Kb FIFO 36 Kb FIFO
4k entries by 4 bits 8k entries by 4 bits 4k + 1 entries by 4 bits 8k + 1 entries by 4 bits
2k entries by 9 bits 4k entries by 9 bits 2k + 1 entries by 9 bits 4k + 1 entries by 9 bits
1k entries by 18 bits 2k entries by 18 bits 1k + 1 entries by 18 bits 2k + 1 entries by 18 bits
512 entries by 36 bits 1k entries by 36 bits 512 + 1 entries by 36 bits 1k + 1 entries by 36 bits
512 entries by 72 bits 512 + 1 entries by 72 bits
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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