RAM 8.0 BUX II Series Guía de usuario Pagina 39
- Pagina / 86
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
7 Series FPGAs Memory Resources www.xilinx.com 39
UG473 (v1.11) November 12, 2014
Block RAM Timing Model
Block RAM Timing Model
This section describes the timing parameters associated with the block RAM in
7 series devices (illustrated in Figure 1-15). The switching characteristics section in the
7 Series FPGAs Data Sheets and the Timing Analyzer (TRCE) report from Xilinx software are
also available for reference.
Block RAM Timing Parameters
Table 1-18 shows the 7 series FPGAs block RAM timing parameters.
X-Ref Target - Figure 1-14
Figure 1-14: Block RAM Reset Operation in Latch Mode
DBRAM = DO
CLK
RAMEN
RSTLAT
D1 D3D0
SRVAL(1LAT)
UG473_c1_14_040411
RSTLAT needs RAMEN = 1
to reset the output of the latch
Table 1-18: Block RAM Timing Parameters
Parameter Function
Control
Signal
Description
Setup and Hold Relative to Clock (CLK)
T
RxCK_x
= Setup time (before clock edge) and T
RCKx_x
= Hold time (after clock edge)
T
RCCK_ADDR
Address inputs ADDR
Time before the clock that address signals must be stable at the
ADDR inputs of the block RAM.
(1)
T
RCKC_ADDR
Time after the clock that address signals must be stable at the ADDR
inputs of the block RAM.
(1)
T
RDCK_DI
Data inputs DI
Time before the clock that data must be stable at the DI inputs of the
block RAM.
T
RCKD_DI
Time after the clock that data must be stable at the DI inputs of the
block RAM.
T
RCCK_RDEN
Enable EN
Time before the clock that the enable signal must be stable at the EN
input of the block RAM.
T
RCKC_RDEN
Time after the clock that the enable signal must be stable at the EN
input of the block RAM.
T
RCCK_RSTREG
T
RCCK_RSTRAM
Synchronous
Set/Reset
RSTREG
RSTRAM
Time before the clock that the synchronous set/reset signal must be
stable at the RST input of the block RAM.
T
RCKC_RSTREG
T
RCKC_RSTRAM
Time after the clock that the synchronous set/reset signal must be
stable at the RST input of the block RAM.
T
RCCK_WEA
Write Enable WE
Time before the clock that the write enable signal must be stable at
the WE input of the block RAM.
T
RCKC_WEA
Time after the clock that the write enable signal must be stable at the
WE input of the block RAM.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
Relacionado con productos y manuales para Amplificadores de audio RAM 8.0 BUX II Series
Amplificadores de audio RAM 1.4 Especificaciones
(19 paginas)
(19 paginas)
Amplificadores de audio RAM 4.0 Manual de usuario
(38 paginas)
(38 paginas)
Amplificadores de audio RAM 7.0 Especificaciones
(28 paginas)
(28 paginas)
Amplificadores de audio RAM 4000 Manual de usuario
(14 paginas)
(14 paginas)
Amplificadores de audio RAM 7.0 Guía de usuario
(118 paginas)
(118 paginas)
Amplificadores de audio RAM 3004 Manual de usuario
(15 paginas)
(15 paginas)
Amplificadores de audio RAM V-6000 Manual de usuario
(24 paginas)
(24 paginas)
Amplificadores de audio RAM 3000 Manual de usuario
(14 paginas)
(14 paginas)
Amplificadores de audio RAM 3000 Especificaciones
(28 paginas)
(28 paginas)
Amplificadores de audio RAM 12000V Información técnica
(105 paginas)
(105 paginas)
Amplificadores de audio RAM 6004 Especificaciones
(106 paginas)
(106 paginas)
Amplificadores de audio RAM 6000V Manual de usuario
(272 paginas)
(272 paginas)
Amplificadores de audio RAM 6000V Información técnica
(145 paginas)
(145 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.072 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales