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UG473 (v1.11) November 12, 2014

Chapter 2: Built-in FIFO Support

REGCE Input Output register clock enable. Only used when

EN_SYNC = TRUE and DO_REG = 1. RSTREG has priority

over REGCE.

DO Output Data output, synchronous to RDCLK.

DOP Output Parity-bit output, synchronous to RDCLK.

FULL Output All entries in FIFO memory are filled. No additional writes

are accepted. Synchronous to WRCLK.

ALMOSTFULL Output Almost all entries in FIFO memory have been filled. The

number of available entries in the FIFO is less than the

ALMOST_FULL_OFFSET value. Synchronous to WRCLK.

The offset for this flag is user configurable. See Table 2-4 for

the clock latency for flag deassertion.

EMPTY Output FIFO is empty. No additional reads are accepted.

Synchronous to RDCLK.

ALMOSTEMPTY Output Almost all valid entries in FIFO have been read. The number

of entries in the FIFO is less than the

ALMOST_EMPTY_OFFSET value. Synchronous with

RDCLK. The offset for this flag is user configurable. See

Table 2-4 for the clock latency for flag deassertion.

RDCOUNT Output The FIFO data read pointer. It is synchronous with RDCLK.

The value wraps around when the maximum read pointer

value is reached.

WRCOUNT Output The FIFO data write pointer. It is synchronous with WRCLK.

The value wraps around when the maximum write pointer

value is reached.

WRERR Output When the FIFO is full, any additional write operation

generates an error flag. Synchronous with WRCLK.

RDERR Output When the FIFO is empty, any additional read operation

generates an error flag. Synchronous with RDCLK.

Table 2-3: FIFO I/O Port Names and Descriptions (Cont’d)

Port Name Direction Description

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 85 86

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RAM 8.0 BUX II Series Guía de usuario Pagina 50