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12 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 1: Block RAM Resources
• 18, 36, or 72-bit wide block RAM ports can have an individual write enable per byte.
This feature is popular for interfacing to a microprocessor.
• Each block RAM contains optional address sequencing and control circuitry to
operate as a built-in dual-clock FIFO memory. In the 7 series architecture, the block
RAM can be configured as an 18 Kb or 36 Kb FIFO.
• All inputs are registered with the port clock and have a setup-to-clock timing
specification.
• All outputs have a read function or a read-during-write function, depending on the
state of the write enable (WE) pin. The outputs are available after the clock-to-out
timing interval. The read-during-write outputs have one of three operating modes:
WRITE_FIRST, READ_FIRST, and NO_CHANGE.
• A write operation requires one clock edge.
• A read operation requires one clock edge.
• All output ports are latched or registered (optional). The state of the output port does
not change until the port executes another read or write operation. The default block
RAM output is latch mode.
• The output datapath has an optional internal pipeline register. Using the register
mode is strongly recommended. This allows a higher clock rate; however, it adds a
clock cycle latency of one.
The 7 series FPGAs block RAM usage rules include:
• The synchronous set/reset (RSTRAM) ports cannot be used when the ECC decoder is
enabled (EN_ECC_READ = TRUE).
• The block RAM synchronous output registers (optional) are set or reset (SRVAL) with
RSTREG when DO_REG = 1. The RSTREG_PRIORITY attribute determines if
RSTREG has priority over REGCE. The synchronous output latches are set or reset
(SRVAL) with RSTRAM when DO_REG is 0 or 1.
• The setup time of the block RAM address and write enable pins must not be violated.
Violating the address setup time (even if write enable is Low) can corrupt the data
contents of the block RAM.
• The block RAM register mode RSTREG requires REGCE = 1 to reset the output DO
register value; if the RSTREG_PRIORITY is set to REGCE. The block RAM array data
output latch does not get reset in this mode. The block RAM latch mode RSTRAM
requires the block RAM enable, EN = 1, to reset the output DO latch value.
• There are two block RAM primitives: RAMB36E1 and RAMB18E1. The RAM_MODE
attribute determines the mode of the block RAM, either SDP mode or true dual-port
(TDP) mode.
• Different read and write port width choices are available when using specific block
RAM primitives. The parity bits are only available for the x9, x18, and x36 port
widths. The parity bits should not be used when the read width is x1, x2, or x4. If the
read width is x1, x2 or x4, the effective write width is x1, x2, x4, x8, x16, or x32.
Similarly, when a write width is x1, x2, or x4, the actual available read width is x1, x2,
x4, x8, x16, or x32 even though the primitive attribute is set to 1, 2, 4, 9, 18, or 36,
respectively. Table 1-1 shows some possible scenarios.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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