RAM 8.0 BUX II Series Guía de usuario Pagina 66

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 86
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 65
66 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 2: Built-in FIFO Support
Connecting FIFOs in Parallel to Increase Width
As shown in Figure 2-12, the 7 series FPGAs FIFO36 can be connected to add width to the
design. CLB logic is used to implement the AND/OR gates. All the FIFO FULL signals
must be ORed together to created the output FULL signal and all the FIFO EMPTY signals
must be ORed together to created the output EMPTY signal. The maximum frequency is
limited by the logic gate feedback path.
X-Ref Target - Figure 2-12
Figure 2-12: Example: Connecting FIFOs in Parallel to Increase Width
RDCLK
WRCLK
DIN[71:0]
RDEN
WREN
RDCLK
WRCLK
DIN[71:0]
DOUT[71:0]
EMPTY
RDEN
WREN
FULL
DOUT[71:0]
EMPTY
FULL
DIN[71:0]
DIN[143:72]
DOUT[71:0]
DOUT[143:72]
RDEN
WREN
WRCLK
RDCLK
512 x 144 FIFO
FIFO #1
FIFO #2
FULL
EMPTY
UG473_c2_12_052610
Vista de pagina 65
1 2 ... 61 62 63 64 65 66 67 68 69 70 71 ... 85 86

Comentarios a estos manuales

Sin comentarios