RAM 8.0 BUX II Series Guía de usuario descargar pdf (Pagina 52)

52 www.xilinx.com 7 Series FPGAs Memory Resources

UG473 (v1.11) November 12, 2014

Chapter 2: Built-in FIFO Support

Empty Flag

The Empty flag is synchronous with RDCLK, and is asserted when the last entry in the

FIFO is read. When there are no more valid entries in the FIFO queue, the read pointer is

frozen. The Empty flag is deasserted after three (in standard mode) or four (in FWFT

mode) read clock cycles after new data is written into the FIFO.

The empty flag is used in the read clock domain. The rising edge of EMPTY is inherently

synchronous with RDCLK. The empty condition can only be terminated by WRCLK,

usually asynchronous to RDCLK. The falling edge of EMPTY must, therefore, artificially

be moved onto the RDCLK time domain. Because the two clocks have an unknown phase

relationship, it takes several cascaded flip-flops to guarantee that such a move does not

cause glitches or metastable problems. The falling edge of EMPTY is thus delayed by

several RDCLK periods after the first write into the previously empty FIFO. This delay

guarantees proper operation under all circumstances, and causes an insignificant loss of

performance after the FIFO had gone empty.

Almost Empty Flag

The Almost Empty flag is set when the FIFO contains the number of entries specified by

the ALMOST_EMPTY_OFFSET value or fewer entries. The Almost Empty flag warns you

to stop reading. It deasserts when the number of entries in the FIFO is greater than the

ALMOST_EMPTY_OFFSET value. Assertion and deassertion is synchronous to RDCLK.

Flag latency is described in Table 2-4.

Read Error Flag

After the Empty flag has been asserted, any further read attempts do not increment the

read address pointer but do trigger the Read Error flag. The Read Error flag is deasserted

when Read Enable or Empty is deasserted Low. The Read Error flag is synchronous to

RDCLK.

Table 2-4: Dual-Clock FIFO Flag Assertion and Deassertion Latency

Status Flag

Clock Cycle Latency

(1)

Assertion Deassertion

Standard FWFT Standard FWFT

Empty

(2)

0034

Full

(2)

0033

Almost Empty

(3)

1144

Almost Full

(3)

1144

Read Error 0000

Write Error 0000

Notes:

1. Latency is with respect to RDCLK or WRCLK.

2. Depending on the offset between read and write clock edges, the Empty and Full flags can deassert

one cycle later.

3. Depending on the offset between read and write clock edges, the Almost Empty and Almost Full flags

can deassert one cycle later.

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 85 86

Comentarios a estos manuales

Sin comentarios

RAM 8.0 BUX II Series Guía de usuario Pagina 52

Comentarios a estos manuales

Relacionado con productos y manuales para Amplificadores de audio RAM 8.0 BUX II Series