RAM 8.0 BUX II Series Guía de usuario Pagina 48

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48 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 2: Built-in FIFO Support
FIFO Architecture: a Top-Level View
Figure 2-2 shows a top-level view of the 7 series FPGAs FIFO architecture. The read
pointer, write pointer, and status flag logic are dedicated for FIFO use only.
FIFO Primitives
Figure 2-3 shows the FIFO36E1 in FIFO36_72 mode.
X-Ref Target - Figure 2-2
Figure 2-2: Top-Level View of FIFO in Block RAM
Block
RAM
WRCOUNT RDCOUNT
WRCLK
WREN
RDCLK
DO/DOPDIN/DINP
RDEN
RST
Status Flag
Logic
FULL
EMPTY
ALMOSTFULL
ALMOSTEMPTY
RDERR
WRERR
waddr raddr
oe
mem_ren
mem_wen
Write
Pointer
Read
Pointer
UG473_c2_02_052610
X-Ref Target - Figure 2-3
Figure 2-3: FIFO36
DOP[7:0]
DI[63:0]
DIP[7:0]
RDEN
RST
RDCLK
WREN
WRCLK
DO[63:0]
RDCOUNT[12:0]
WRCOUNT[12:0]
EMPTY
FULL
ALMOSTEMPTY
ALMOSTFULL
WRERR
RDERR
FIFO36
UG473_c2_03_052610
RSTREG
REGCE
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