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7 Series FPGAs Memory Resources www.xilinx.com 61
UG473 (v1.11) November 12, 2014
FIFO Timing Models and Parameters
Clock Event 3: Write Operation and Assertion of Write Error Signal
The write error signal pin is asserted when data going into the FIFO is not written because
the FIFO is in a Full state.
• At time T
RDCK_DI
, before clock event 3 (WRCLK), data 05 becomes valid at the DI
inputs of the FIFO.
• Write enable remains asserted at the WREN input of the FIFO.
• At time T
RCKO_WRERR
, after clock event 3 (WRCLK), a write error is asserted at the
WRERR output pin of the FIFO. Data 05 is not written into the FIFO.
Clock Event 4: Write Operation and Deassertion of Write Error Signal
The write error signal pin is deasserted when you stop trying to write into a full FIFO.
•At time T
RCCK_WREN
, before clock event 4 (WRCLK), write enable is deasserted at the
WREN input of the FIFO.
• At time T
RCKO_WRERR
, after clock event 4 (WRCLK), write error is deasserted at the
WRERR output pin of the FIFO.
The write error signal is asserted/deasserted at every write-clock positive edge. As long as
both the write enable and Full signals are true, write error remains asserted.
Case 3: Reading from a Full FIFO
Prior to the operations performed in Figure 2-8, the FIFO is completely full.
Clock Event 1 and Clock Event 2: Read Operation and Deassertion of Full Signal
During a read operation on a full FIFO, the content of the FIFO at the first address is
asserted at the DO output pins of the FIFO. The FULL pin is deasserted three WRCLK
cycles after the first read. This is a different behavior from Virtex-6 FPGA functionality.
The example in Figure 2-8 reflects both standard and FWFT modes. Clock event 1 is with
respect to read-clock. Clock event 2 appears three write-clock cycles after clock event 1.
• At time T
RCCK_RDEN
, before clock event 1 (RDCLK), read enable becomes valid at the
RDEN input of the FIFO.
X-Ref Target - Figure 2-8
Figure 2-8: Reading From a Full FIFO
UG473_c2_08_032111
142
020100 03 04 05 06
3
WRCLK
WREN
RDCLK
RDEN
DO
FULL
AFULL
T
RCCK_RDEN
T
RCKO_DO
T
RCKO_AFULL
T
RCKO_FULL
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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