RAM 8.0 BUX II Series Guía de usuario Pagina 3
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UG473 (v1.11) November 12, 2014 www.xilinx.com 7 Series FPGAs Memory Resources
01/30/2012 1.5 In Table 1-2, removed XC7A8, XC7A15, XC7A30T, and XC7A50T; updated number of
36 Kb block RAM blocks per column for XC7K420T and XC7VX550T; updated note 1 to
say “GTP/GTX Quad.”
Updated Simple Dual-Port Block RAM.
07/04/2012 1.6 Updated fifth and sixth bullets in Changes from Virtex-6 FPGAs.
Added Virtex-7 devices to Table 1-2. Updated descriptions of RAMB36E1, RAMB18E1,
and FIFO18E1 in Table 1-6.
Updated description of WREN in Table 2-3. In Table 2-9, replaced T
RCCK_RST
/T
RCKC_RST
with T
RREC_RST
/T
RREM_RST
.
10/02/2012 1.7 Removed XC7A350T, XC7V1500T, and XC7VH290T from Table 1-2.
08/07/2013 1.8 Added three devices to Table 1-2.
10/02/2013 1.9 Update disclaimer and copyright on page 2. Updated Byte-Wide Write Enable.
01/30/2014 1.10 Updated the last bullet in Summary. Updated Figure 1-6 and Figure 3-2.
05/09/2014 1.10.1 Typographical updates in Table 1-7 and Table 1-8.
11/12/2014 1.11 Added XC7A15T device to Table 1-2.
Date Version Revision
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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