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26 www.xilinx.com 7 Series FPGAs Memory Resources

UG473 (v1.11) November 12, 2014

Chapter 1: Block RAM Resources

Block RAM Port Signals

Each block RAM port operates independently of the other while accessing the same set of

36 Kbit memory cells.

Clock - CLKARDCLK and CLKBWRCLK

Each port is fully synchronous with independent clock pins. All port input pins have setup

time referenced to the port CLK pin. The output data bus has a clock-to-out time

referenced to the CLK pin. Clock polarity is configurable (rising edge by default). In SDP

mode, the CLKA port is the RDCLK and the CLKB port is the WRCLK.

Enable - ENARDEN and ENBWREN

The enable pin affects the read, write, and set/reset functionality of the port. Ports with an

inactive enable pin keep the output pins in the previous state and do not write data to the

memory cells. Enable polarity is configurable (active-High by default). In SDP mode, the

ENA port is the RDEN and the ENB port is the WREN.

Byte-Wide Write Enable - WEA and WEBWE

To write the content of the data input bus into the addressed memory location, both EN

and WE must be active within a setup time before the active clock edge. The output latches

are loaded or not loaded according to the write configuration (WRITE_FIRST,

READ_FIRST, NO_CHANGE). When WE is inactive and EN is active, a read operation

occurs, and the contents of the memory cells referenced by the address bus appear on the

data-out bus, regardless of the write mode attribute. Write enable polarity is not

configurable (active-High). In SDP mode, the WEBWE[7:0] port is the byte-write enable. In

TDP mode, the WEA[3:0] and WEB[3:0] are byte-write enables for port A and port B,

respectively.

RSTRAMB Synchronous output latch set/reset as initialized by SRVAL_B (DOB_REG = 0).

CLKARDCLK Port A clock input. In RAM_MODE = SDP, this is the RDCLK.

CLKBWRCLK Port B clock input. In RAM_MODE = SDP, this is the WRCLK.

REGCEAREGCE Port A output register clock enable (DOA_REG = 1). In RAM_MODE = SDP, this is the REGCE.

REGCEB Port B output register clock enable (DOB_REG = 1).

DOADO[15:0] Port A data output bus addressed by ADDRARDADDR. See Table 1-13 for SDP mode port name

mapping.

DOPADOP[1:0] Port A parity output bus addressed by ADDRARDADDR. See Table 1-13 for SDP mode port name

mapping.

DOBDO[15:0] Port B data output bus addressed by ADDRBWRADDR. See Table 1-13 for SDP mode port name

mapping.

DOPBDOP[1:0] Port B parity output bus addressed by ADDRBWRADDR. See Table 1-13 for SDP mode port name

mapping.

Table 1-8: RAMB18E1 Port Names and Descriptions (Cont’d)

Port Name Description

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 85 86

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RAM 8.0 BUX II Series Guía de usuario Pagina 26