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UG473 (v1.11) November 12, 2014
Chapter 3: Built-in Error Correction
RSTREGB Synchronous output register set/reset as initialized by SRVAL_B (DO_REG = 1).
RSTREG_PRIORITY_B determines the priority over REGCE. In SDP (ECC) mode, connect
RSTREGB to GND.
RSTRAMARSTRAM Synchronous output latch set/reset as initialized by SRVAL_A (DO_REG = 0). In
RAM_MODE = SDP, this is the RSTRAM. In ECC mode, connect to GND.
RSTRAMB Synchronous output latch set/reset as initialized by SRVAL_B (DO_REG = 0). In SDP (ECC)
mode, connect REGCEB to GND.
CLKARDCLK Port A clock input. In RAM_MODE = SDP this is the RDCLK.
CLKBWRCLK Port B clock input. In RAM_MODE = SDP this is the WRCLK.
REGCEAREGCE Port A output register clock enable (DO_REG = 1). In RAM_MODE SDP and ECC, this is the
REGCE.
REGCEB Port B output register clock enable (DO_REG = 1). In ECC mode, connect REGCEB to GND.
CASCADEINA Port A cascade input. Used in RAM_MODE = TDP only.
CASCADEINB Port B cascade input. Used in RAM_MODE = TDP only.
CASCADEOUTA Port A cascade output. Used in RAM_MODE = TDP only.
CASCADEOUTB Port B cascade output. Used in RAM_MODE = TDP only.
DOADO[31:0] Port A data output bus addressed by ADDRARDADDR. See Table 1-13 for SDP mode port
name mapping.
DOPADOP[3:0] Port A parity output bus addressed by ADDRARDADDR. See Table 1-13 for SDP mode port
name mapping.
DOBDO[31:0] Port B Data output bus addressed by ADDRARDADDR. See Table 1-13 for SDP mode port
name mapping.
DOPBDOP[3:0] Port B parity output bus addressed by ADDRARDADDR. See Table 1-13 for SDP mode port
name mapping.
ECC Port Names (Not used if RAM_MODE = TDP)
INJECTSBERR Inject single-bit error if ECC is used. Creates a single-bit error at a particular block RAM bit
location when asserted during write. The block RAM ECC logic corrects this error when this
location is read back. The error is created in bit DI[30].
INJECTDBERR Inject double-bit error if ECC is used. Creates a double-bit error at two particular block RAM
bit locations when asserted during write. The block RAM ECC logic flags a double-bit error
when this location is read back. When both INJECTSBERR and INJECTDBERR signals are
simultaneously asserted, then a double-bit error is injected. The errors are created in bits
DI[30] and DI[62].
ECCPARITY[7:0] ECC encoder output bus for ECC used in encode-only mode.
SBITERR ECC single-bit error output status.
DBITERR ECC double-bit error output status.
RDADDRECC[8:0] ECC read address. Address pointer to the data currently read out. The data and
corresponding address are available in the same cycle.
Notes:
1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error
detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and
DBITERR indicate these three conditions.
Table 3-1: RAMB36E1 Port Names and Descriptions Including ECC Ports (Cont’d)
Port Name Signal Description
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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