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24 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 1: Block RAM Resources
Table 1-7 and Table 1-8 show the show the port names and descriptions of the primitives
outlined in Table 1-6. The ECC ports are described in Chapter 3, Built-in Error Correction.
Table 1-6: 7 Series FPGAs Block RAM and FIFO Primitives
Primitive Description
RAMB36E1 In TDP mode, supports port widths of x1, x2, x4, x9, x18, x36
In SDP mode, the Read or Write port width is x64 or x72. Alternate port is x1, x2, x4, x9, x18, x36, x72.
In ECC mode, supports 64-bit ECC encoding and decoding
RAMB18E1 In TDP mode, supports port widths of x1, x2, x4, x9, x18
In SDP mode, the Read or Write port width is x32 or x36. Alternate port is x1, x2, x4, x9, x18, x36.
FIFO36E1 In FIFO36 mode, supports port widths of x4, x9, x18, x36
In FIFO36_72 mode, port width is x72, optional ECC support.
FIFO18E1 In FIFO18 mode, supports port widths of x4, x9, x18
In FIFO18_36 mode, port width is x36
Table 1-7: RAMB36E1 Port Names and Descriptions
Port Name Description
DIADI[31:0] Port A data inputs addressed by ADDRARDADDR. See Table 1-13 for SDP mode port name
mapping.
DIPADIP[3:0] Port A data parity inputs addressed by ADDRARDADDR. See Table 1-13 for SDP mode port name
mapping.
DIBDI[31:0] Port B data inputs addressed by ADDRBWRADDR. See Table 1-13 for SDP mode port name
mapping.
DIPBDIP[3:0] Port B data parity inputs addressed by ADDRBWRADDR. See Table 1-13 for SDP mode port name
mapping.
ADDRARDADDR [15:0] Port A address input bus. In RAM_MODE = SDP, this is the RDADDR bus.
ADDRBWRADDR[15:0] Port B address input bus. In RAM_MODE = SDP, this is the WRADDR bus.
WEA[3:0] Port A byte-wide Write enable. Not used in RAM_MODE = SDP.
WEBWE[7:0] Port B byte-wide Write enable. In RAM_MODE = SDP, this is the byte-wide Write enable.
ENARDEN Port A enable. In RAM_MODE = SDP, this is the RDEN.
ENBWREN Port B enable. In RAM_MODE = SDP, this is the WREN.
RSTREGARSTREG Synchronous output register set/reset as initialized by SRVAL_A (DOA_REG = 1).
RSTREG_PRIORITY_A determines the priority over REGCE. In RAM_MODE = SDP, this is the
RSTREG.
RSTREGB Synchronous output register set/reset as initialized by SRVAL_B (DOB_REG = 1).
RSTREG_PRIORITY_B determines the priority over REGCE.
RSTRAMARSTRAM Synchronous output latch set/reset as initialized by SRVAL_A (DOA_REG = 0). In
RAM_MODE = SDP, this is the RSTRAM.
RSTRAMB Synchronous output latch set/reset as initialized by SRVAL_B (DOB_REG = 0).
CLKARDCLK Port A clock input. In RAM_MODE = SDP, this is the RDCLK.
CLKBWRCLK Port B clock input. In RAM_MODE = SDP, this is the WRCLK.
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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