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LogiCORE IP Block Memory Generator v6.1

98 www.xilinx.com DS512 March 1, 2011

Product Specification

Kintex-7, Virtex-7, and Virtex-6 FPGAs: Memory with Primitive Output Registers and

without Special Reset Behavior option

If Use RSTA Pin (set/reset pin) or Use RSTB Pin (set/reset pin) is selected, and the special reset

behavior (to reset the memory latch besides the primitive output register) is not selected, then the input

reset signal is only connected to the RSTREG pin of the Kintex-7, Virtex-7, and Virtex-6 devices’ block

RAM primitive, as illustrated in Figure 65.

Note:

This will result in reset similar to that of Spartan-3, Spartan-3A, Virtex-5 and Virtex-4 devices.

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

 Use RSTA Pin (set/reset pin)  Use RSTB Pin (set/reset pin)

 Reset Memory Latch  Reset Memory Latch

X-Ref Target - Figure 65

Figure 65: Kintex-7, Virtex-7, and Virtex-6 Block Memory Generated with Register Port [A|B]

Output of Memory Primitives Enabled and without Special Reset Behavior

Block Memory Generator Core

Latches

Utilized Block RAM Primitives

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

Use REGCE Pin

REGCE

MUX

CLK

RST

DOUT

S* : The synchronous reset (S) of the flop is gated by CE

RSTRAM

RSTREG

FALSE

TRUE

‘0’

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 117 118

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RAM 7.0 Guía de usuario Pagina 98

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