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DS512 March 1, 2011 www.xilinx.com 9

Product Specification

LogiCORE IP Block Memory Generator v6.1

Supported Devices

AXI4 BMG Core Channel Handshake Sequence

Figure 9 and Figure 10 illustrates an example handshake sequence for AXI4 BMG core. Figure 9

illustrates single burst Write operations to block RAM. By default the AWREADY signal is asserted on the

bus so that the address can be captured immediately during the clock cycle when both AWVALID and

AWREADY are asserted. (With the default set in this manner, there is no need to wait an extra clock cycle

AWREADY to be asserted first.) By default, the WREADY signal will be de-asserted. Upon detecting

AWVALID being asserted, the WREADY signal will be asserted (AXI4 BMG core has registered an AXI

Address and is ready to accept Data), and when WVALID is also asserted, writes will be performed to

the block RAM. If the write data channel (WVALID) is presented prior to the write address channel valid

(AWVALID) assertion, the write transactions will not be initiated until the write address channel has

valid information.

The AXI4 Block Memory core will assert BVALID for each transaction only after the last data transfer is

accepted. The core also will not wait for the master to assert BREADY before asserting BVALID.

Table 2: AXI4 BMG Supported FPGA Families and Sub-Families

FPGA Family Sub-Family

Spartan-6 LX/LXT

Virtex-6 CXT/HXT/LXT/SXT

Virtex-7

Kintex-7

X-Ref Target - Figure 9

Figure 9: AXI4-Lite Single Burst Write Transactions

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