RAM 7.0 Guía de usuario descargar pdf (Pagina 34)

LogiCORE IP Block Memory Generator v6.1

34 www.xilinx.com DS512 March 1, 2011

Product Specification

For Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A DSP FPGAs, the Register

Port [A|B] Output of Memory Primitives option may be implemented using the embedded block RAM

registers, requiring no further FPGA resources. All other register stages are implemented in FPGA

fabric. Figure 35 shows an example of a Kintex-7, Virtex-7, Virtex-6, Virtex-5 or Virtex-4 FPGA-based

memory that has been configured using both output register stages for one of the ports.

When using the Synchronous Reset Input (RST), the behavior of the embedded output registers in the

Spartan-3A DSP FPGA differs slightly from the configuration shown in Figure 35. By default, the Block

Memory Generator builds the memory output register in the FPGA fabric to maintain functionality

compatibility with Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA configurations. To force the

core to use the embedded output registers in Spartan-6 and Spartan-3A DSP devices, the Reset

Behavior options are provided. For a complete description of the supported output options, see Output

Optional Pipeline Stages

The Block Memory Generator core allows optional pipeline stages within the MUX, which may

improve core performance. Users can add up to three pipeline stages within the MUX, excluding the

registers at the output of the core. This optional pipeline stages option is available only when the

registers at the output of the memory core are enabled and when the constructed memory has more

than one primitive in depth, so that a MUX is needed on the output.

X-Ref Target - Figure 35

Figure 35: Kintex-7, Virtex-7, Virtex-6, Virtex-5, and Virtex-4 Block Memory with Register Port

[A|B] Output of Memory Primitives and Register Port [A|B] Output of

Memory Core Options Enabled

Block Memory Generator Core

Core

Output

Registers

Latches

FALSE

Block RAM Primitives

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

Use REGCE Pin

REGCE

MUX

CLK

RST

DOUT

R* : The reset (R) of the flop is gated by CE

TRUE

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 117 118

Comentarios a estos manuales

Sin comentarios

RAM 7.0 Guía de usuario Pagina 34

Comentarios a estos manuales

Relacionado con productos y manuales para Amplificadores de audio RAM 7.0