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DS512 March 1, 2011 www.xilinx.com 37

Product Specification

LogiCORE IP Block Memory Generator v6.1

Optional Set/Reset Pins

The set/reset pins (RSTA and RSTB) control the reset operation of the last register in the output stage.

For memories with no output registers, the reset pins control the memory output latches.

When

RST and REGCE are asserted on a given port, the data on the output of that port is driven to the

reset value defined in the CORE Generator GUI. (The reset occurs on RST and EN when the Use REGCE

Pin option is not selected.)

• For Virtex-4 FPGAs, if the option to use the set/reset pin is selected in conjunction with memory

primitive registers and without core output registers, the Virtex-4 embedded block RAM registers

are not utilized for the corresponding port and are implemented in the FPGA logic instead.

• For Kintex-7, Virtex-7, Virtex-6, Spartan-6, and Spartan-3A DSP FPGAs, the set/reset behavior

differs when the reset behavior option is selected. However, this option saves resources by using

the embedded output registers available in the Spartan-6 and Spartan-3A DSP primitives. See

Special Reset Behavior, page 39 for more information.

Memory Output Flow Control

The combination of the enable (EN), reset (RST), and register enable (REGCE) pins allow a wide range

of data flows in the output stage. Figure 37 and Figure 38 are examples on how this can be

accomplished. Keep in mind that the

RST and REGCE pins apply only to the last register stage.

Figure 37 depicts how

RST can be used to control the data output to allow only intended data through.

Assume that both output registers are used for port A, the port A reset value is 0xFFFF, and that

EN and

REGCE are always asserted. The data on the block RAM memory latch is labeled LATCH, while the

output of the block RAM embedded register is labeled REG1. The output of the last register is the

output of the core,

DOUT.

X-Ref Target - Figure 37

Figure 37: Flow Control Using RST

REG1

CLKA

ADDRA[7:0]

AA BB CC

data(AA) data(BB)

RST

LATCH

data(AA) data(BB) data(CC)

DOUT

data(AA) data(BB)

FFFFFFFF

data(CC)

data(DD)

data(CC) FFFF

data(DD)

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 117 118

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