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LogiCORE IP Block Memory Generator v6.1

2 www.xilinx.com DS512 March 1, 2011

Product Specification

Features

Features Common to the Native Interface and AXI4 BMG Cores

• Optimized algorithms for minimum block RAM resource utilization or low power utilization

• Configurable memory initialization

• Individual Write enable per byte in Kintex™-7, Virtex®-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6,

and Spartan-3A/XA DSP with or without parity

• Optimized VHDL and Verilog behavioral models for fast simulation times; structural simulation

models for precise simulation of memory behaviors

• Selectable operating mode per port: WRITE_FIRST, READ_FIRST, or NO_CHANGE

• Smaller fixed primitive configurations are now possible in Spartan-6 devices with the introduction

of the new Spartan-6 device 9K primitives

• Lower data widths for Kintex-7, Virtex-7, and Virtex-6 devices in SDP mode

Native Block Memory Generator Specific Features

• Generates Single-port RAM, Simple Dual-port RAM, True Dual-port RAM, Single-port ROM, and

Dual-port ROM

• Supports data widths from 1 to 1152 bits and memory depths from 2 to 9M words (limited only by

memory resources on selected part)

• Configurable port aspect ratios for dual-port configurations and Read-to-Write aspect ratios in

Virtex-6, Virtex-5, and Virtex-4 FPGAs

• Supports the built-in Hamming Error Correction Capability (ECC) available in Kintex-7, Virtex-7,

Virtex-6 and Virtex-5 devices for data widths greater than 64 bits. Error injection pins in Kintex-7,

Virtex-7, and Virtex-6 allow insertion of single and double-bit errors

• Supports soft Hamming Error Correction (Soft ECC) in Kintex-7, Virtex-7, Virtex-6, and Spartan-6

devices for data widths less than 64 bits.

• Option to pipeline DOUT bus for improved performance in specific configurations

• Choice of reset priority for output registers between priority of SR (Set Reset) or CE (Clock Enable)

in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 families

• Asynchronous reset in Spartan-6 devices

• Performance up to 450 MHz

AXI4 Interface Block Memory Generator Specific Features

• Supports AXI4 and AXI4-Lite interface protocols

• AXI4 compliant Memory and Peripheral Slave types

• Independent Read and Write Channels

• Zero delay datapath

• Supports registered outputs for handshake signals

• INCR burst sizes up to 256 data transfers

• WRAP bursts of 2, 4, 8, and 16 data beats

• AXI narrow and unaligned burst transfers

• Simple Dual-port RAM primitive configurations

• Performance up to 300 MHz

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