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DS512 March 1, 2011 www.xilinx.com 19

Product Specification

LogiCORE IP Block Memory Generator v6.1

Optional Pipeline Stages

Pipeline stages are currently not supported.

Memory Initialization Capability

The memory contents can be optionally initialized using a memory coefficient (COE) file or by

specifying a default data value. A COE file can define the initial contents of each individual memory

location, while the default data value option defines the initial content for all locations.

Simulation Models

The Block Memory Generator core provides behavioral and structural simulation models in VHDL and

Verilog to give the user the option to perform either simple or precise modeling of memory behaviors,

respectively.

Block Memory Generator Functional Description

The Block Memory Generator is used to build custom memory modules from block RAM primitives in

Xilinx FPGAs. The core implements an optimal memory by arranging block RAM primitives based on

user selections, automating the process of primitive instantiation and concatenation. Using the CORE

Generator Graphical User Interface (GUI), users can configure the core and rapidly generate a highly

optimized custom memory solution.

Memory Type

The Block Memory Generator creates five memory types: Single-port RAM, Simple Dual-port RAM,

True Dual-port RAM, Single-port ROM, and Dual-port ROM. Figure 18 through Figure 22 illustrate the

signals available for each type. Optional pins are displayed in italics.

For each configuration, optimizations are made within the core to minimize the total resources used.

For example, a Simple Dual-port RAM with symmetric ports can utilize the special Simple Dual-port

RAM primitive in Virtex-5 devices, which can save as much as fifty percent of the block RAM resources

for memories 512 words deep or fewer. The Single-port ROM allows Read access to the memory space

through a single port, as illustrated in Figure 18.

X-Ref Target - Figure 18

Figure 18: Single-port ROM

Single-Port ROM

ADDRA

ENA

RSTA

CLKA

DOUTA

REGCEA

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 117 118

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