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DS512 March 1, 2011 www.xilinx.com 27

Product Specification

LogiCORE IP Block Memory Generator v6.1

• No Change Mode: In NO_CHANGE mode, the output latches remain unchanged during a Write

operation. As shown in Figure 28, the data output is still the previous Read data and is unaffected

by a Write operation on the same port.

Data Width Aspect Ratios

The Block Memory Generator supports data width aspect ratios. This allows the port A data width to

be different than the port B data width, as described in Port Aspect Ratios in the following section. In

Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA-based memories, all four data buses (DINA,

DOUTA, DINB, and DOUTB) can have different widths, as described in Kintex-7, Virtex-7, Virtex-6,

Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios, page 28.

The limitations of the data width aspect ratio feature (some of which are imposed by other optional

features) are described in Aspect Ratio Limitations, page 29. The CORE Generator GUI ensures only

valid aspect ratios are selected.

Port Aspect Ratios

The Block Memory Generator supports port aspect ratios of 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1,

and 32:1. The port A data width can be up to 32 times larger than the port B data width, or vice versa.

The smaller data words are arranged in little-endian format, as illustrated in Figure 29.

Port Aspect Ratio Example

Consider a True Dual-port RAM of 32x2048, which is the A port width and depth. From the perspective

of an 8-bit B port, the depth would be 8192. The

ADDRA bus is 11 bits, while the ADDRB bus is 13 bits.

The data is stored little-endian, as shown in Figure 29. Note that A

is the data word at address n, with

respect to the A port. B

is the data word at address n with respect to the B port. A

is comprised of B

, B

, and B

X-Ref Target - Figure 28

Figure 28: No Change Mode Example

X-Ref Target - Figure 29

Figure 29: Port Aspect Ratio Example Memory Map

WEA

DINA[15:0]

DOUTA[15:0]

CLKA

ADDRA

1111

ENA

cc dd

2222

MEM(aa) MEM(dd)0000

DISABLED READ

WRITE

MEM(bb)=

1111

WRITE

MEM(cc)=

2222

READ

31 0

7 0

. .

7 0

. .

7 0

. .

7 0

. .

7 0

. .

7 0

. .

7 0

. .

7 0

. .

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 117 118

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RAM 7.0 Guía de usuario Pagina 27

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