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Product Specification

LogiCORE IP Block Memory Generator v6.1

AXI4 Interface Block Memory Generator Signal List

AXI4 Interface - Global Signals

AXI4-Interface Signals

DOUTB Output

Port B Data Output: Data output from Read operations via Port B. Available

in dual-port configurations.

ENB Input

Port B Clock Enable: Enables Read, Write, and reset operations via Port

B. Optional in dual-port configurations.

WEB Input

Port B Write Enable: Enables Write operations via Port B. Available in Dual-

port RAM configurations.

RSTB Input

Port B Set/Reset: Resets the Port B memory output latch or output register.

Optional in all configurations.

REGCEB Input

Port B Register Enable: Enables the last output register of port B. Optional

in dual-port configurations with port B output registers.

SBITERR Output

Single-Bit Error: Flags the presence of a single-bit error in memory which

has been auto-corrected on the output bus.

DBITERR Output

Double-Bit Error: Flags the presence of a double-bit error in memory.

Double-bit errors cannot be auto-corrected by the built-in ECC decode

module.

INJECTSBITERR

Input

Inject Single-Bit Error: Available only for Kintex-7, Virtex-7, and Virtex-6

ECC configurations.

INJECTDBITERR

Input

Inject Double-Bit Error: Available only for Kintex-7, Virtex-7, and Virtex-6

ECC configurations.

RDADDRECC

Output

Read Address for ECC Error output: Available only for Kintex-7, Virtex-7,

and Virtex-6 ECC configurations.

Table 17: AXI4 or AXI4-Lite- Global Interface Signals

Name Direction Description

AXI4 or AXI4-Lite Global Interface Signals

S_ACLK Input

Global Slave Interface Clock: All signals are sampled on the rising edge of

this clock.

S_ARESETN Input Global Reset: This signal is active low.

Table 18: AXI4 Write Channel Interface Signals

Name Direction Description

AXI4 Write Address Channel Interface Signals

S_AXI_AWID[m:0] Input

Write Address ID. This signal is the identification tag for the Write address

group of signals.

Write address ID is optional for Memory Slave configuration and is not

supported for Peripheral Slave configuration.

S_AXI_AWADDR[31:0] Input

Write Address. The Write address bus gives the address of the first

transfer in a Write burst transaction. The associated control signals are

used to determine the addresses of the remaining transfers in the burst.

Table 16: Core Signal Pinout (Cont’d)

Name Direction Description

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 117 118

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