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DS512 March 1, 2011 www.xilinx.com 35

Product Specification

LogiCORE IP Block Memory Generator v6.1

The pipeline stages are common for port A and port B and can be a value of 1, 2, or 3 if the Register

Output of Memory Core option is selected in the GUI for both port A and port B. Note that each

pipeline stage adds an additional clock cycle of latency to the Read operation.

If the configuration has BuiltIn_ECC (ECC), the SBITERR and DBITERR outputs are delayed to align

with DOUT. Note that adding pipeline stages within the MUX improves performance only if the critical

path in the design is the data through the MUX. The MUX size displayed in the GUI can be used to

determine the number of pipeline stages to use within the MUX. See Optional Output Registers,

page 68 for detailed information. Figure 36 shows a memory configuration with an 8:1 MUX and two

pipeline stages within the MUX. Figure 36 explains how the 8:1 MUX is pipelined internally with two

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RAM 7.0 Guía de usuario Pagina 35