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LogiCORE IP Block Memory Generator v6.1

4 www.xilinx.com DS512 March 1, 2011

Product Specification

Memory Types

The Block Memory Generator core uses embedded block RAM to generate five types of memories:

•Single-port RAM

•Simple Dual-port RAM

• True Dual-port RAM

•Single-port ROM

•Dual-port ROM

For dual-port memories, each port operates independently. Operating mode, clock frequency, optional

output registers, and optional pins are selectable per port. For Simple Dual-port RAM, the operating

modes are not selectable. See Collision Behavior, page 30 for additional information.

Selectable Memory Algorithm

The core configures block RAM primitives and connects them together using one of the following

algorithms:

• Minimum Area Algorithm: The memory is generated using the minimum number of block RAM

primitives. Both data and parity bits are utilized.

• Low Power Algorithm: The memory is generated such that the minimum number of block RAM

primitives are enabled during a Read or Write operation.

• Fixed Primitive Algorithm: The memory is generated using only one type of block RAM

primitive. For a complete list of primitives available for each device family, see the data sheet for

that family.

Configurable Width and Depth

The Block Memory Generator can generate memory structures from 1 to 1152 bits wide, and at least two

locations deep. The maximum depth of the memory is limited only by the number of block RAM

primitives in the target device.

Selectable Operating Mode per Port

The Block Memory Generator supports the following block RAM primitive operating modes: WRITE

FIRST, READ FIRST, and NO CHANGE. Each port may be assigned its own operating mode.

Selectable Port Aspect Ratios

The core supports the same port aspect ratios as the block RAM primitives:

• In all supported device families, the A port width may differ from the B port width by a factor of 1,

2, 4, 8, 16, or 32.

Virtex-5 LXT/FXT/SXT/TXT

Virtex-6 CXT/HXT/LXT/SXT

Virtex-7

Kintex-7

Table 1: Supported FPGA Families and Sub-Families (Cont’d)

FPGA Family Sub-Family

1 2 3 4 5 6 7 8 9 ... 117 118

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