RAM 7.0 Guía de usuario Pagina 52
- Pagina / 118
- Tabla de contenidos
- MARCADORES
- LogiCORE IP Block 1
- Memory Generator v6.1 1
- Features 2
- Overview 3
- Applications 3
- Supported Devices 3
- Memory Types 4
- $;,0DVWHU 8
- :ULWH&KDQQHOV 8
- $;,0DVWHU 8
- 5HDG&KDQQHOV 8
- Product Specification 10
- AXI4 Wrap Burst Support 12
- X-Ref Target - Figure 14 14
- AXI4 Unaligned Transactions 16
- Configurable Width and Depth 17
- Throughput & Performance 18
- Selectable Port Aspect Ratios 18
- Optional Output Register 18
- Optional Pipeline Stages 19
- Simulation Models 19
- Memory Type 19
- Selectable Memory Algorithm 22
- Fixed Primitive Algorithm 23
- Selectable Width and Depth 25
- X-Ref Target - Figure 26 26
- X-Ref Target - Figure 27 26
- X-Ref Target - Figure 30 28
- Collision Behavior 30
- ADDRA = ADDRB = 0 31
- DOUTB is shown for when port 31
- Optional Output Registers 32
- REGCE pin, the last output 36
- EN signal 36
- Optional Set/Reset Pins 37
- Memory Output Flow Control 37
- Disabled ReadReset When 38
- Read No Reset 38
- When EN=’0’ 38
- Operation 39
- ReadReset Read Reset 39
- Asynchronous Reset 41
- 1111 2222 45
- X-Ref Target - Figure 48 48
- Signal Lists 56
- AXI4-Interface Signals 57
- Name Direction Description 58
- AXI4-Lite Interface Signals 60
- ENA pin available) 67
- ENB pin available) 67
- Block RAM Usage 73
- Examples 77
- Output Registers 78
- Aspect Ratios 80
- Algorithm 81
- Low Power Designs 84
- Auto Upgrade Feature 86
- X-Ref Target - Figure 62 87
- Configurations 96
- Core Output Registers 97
- Port A or Port B 100
- Output of Memory Core Enabled 111
- References 116
- Support 117
- Ordering Information 117
- Revision History 117
- Notice of Disclaimer 118
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