RAM 7.0 Guía de usuario descargar pdf (Pagina 105)

DS512 March 1, 2011 www.xilinx.com 105

Product Specification

LogiCORE IP Block Memory Generator v6.1

Spartan-6 or Spartan-3A DSP FPGA: Output Register Configurations

To tailor register options for Spartan-6 or Spartan-3A DSP device configurations, two selections for port

A and two selections for port B are provided on screen 3 of the CORE Generator GUI in the Optional

Output Registers section. The embedded output registers for the corresponding port(s) are enabled

when Register Port [A|B] Output of Memory Primitives is selected. Similarly, registers at the output of

the core for the corresponding port(s) are enabled by selecting Register Port [A|B] Output of Memory

Core. Figure 72 through Figure 77 illustrate the Spartan-6 or Spartan-3A DSP output register

configurations.

When only Register Port [A|B] Output of Memory Primitives and the corresponding Use RST[A|B]

Pin (set/reset pin) is selected, the special reset behavior (option to reset the memory latch besides the

primitive output register) becomes available. This option is displayed as the Reset Memory Latch

option on the Spartan-6 and Spartan-3A DSP GUI. Selecting this option forces the core to use the

Spartan-6 or Spartan-3A DSP embedded output registers, but changes the behavior of the core. For

detailed information, see the sections that follow.

1 2 ... 100 101 102 103 104 105 106 107 108 109 110 ... 117 118

Sin comentarios

RAM 7.0 Guía de usuario Pagina 105