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Product Specification

LogiCORE IP Block Memory Generator v6.1

AXI4-Lite Write Data Channel Interface Signals

S_AXI_WDATA[m-1:0] Input

Write Data. For Memory Slave configurations, the Write data bus can be

32 or 64 bits wide. For Peripheral Slave configurations, the Write data bus

can be 8, 16, 32 or 64 bits wide.

S_AXI_WSTRB[m/8-1:0] Input

Write Strobes. This signal indicates which byte lanes to update in

memory. There is one Write strobe for each eight bits of the Write data bus.

Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)].

S_AXI_WVALID Input

Write Valid. This signal indicates that valid Write data and strobes are

available:

1 = Write data and strobes available

0 = Write data and strobes not available

S_AXI_WREADY Output

Write Ready. This signal indicates that the slave can accept the Write

data:

• 1 = slave ready

• 0 = slave not ready

AXI4-Lite Write Response Channel Interface Signals

S_AXI_BVALID Output

Write Response Valid. This signal indicates that a valid Write response is

available:

• 1 = Write response available

• 0 = Write response not available

S_AXI_BREADY Input

Response Ready. This signal indicates that the master can accept the

response information.

• 1 = Master ready

• 0 = Master not ready

S_AXI_BID[m:0] Output

Response ID. The identification tag of the Write response. The BID value

must match the AWID value of the Write transaction to which the slave is

responding.

Response ID is optional for Memory Slave configuration and is not

supported for Peripheral Slave configuration.

Response ID can be 1 to 16 bits wide.

S_AXI_BRESP[1:0] Output

Write Response. This signal indicates the status of the Write transaction.

The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

Write response is always set to OKAY.

Write response is generated only when AXI4 ID is enabled for Memory

Slave. Write response is not supported for Peripheral Slave configuration.

Table 21: AXI4-Lite Read Channel Interface Signals

Name Direction Description

AXI4-Lite Read Address Channel Interface Signals

S_AXI_ARADDR[31:0] Input

Read Address. The Read address bus gives the initial address of a Read

burst transaction. Only the start address of the burst is provided and the

control signals that are issued alongside the address detail how the address

is calculated for the remaining transfers in the burst.

S_AXI_ARID[m:0] Input

Read Address ID. This signal is the identification tag for the Read address

group of signals.

Read address ID is optional for Memory Slave configuration and is not

supported for Peripheral Slave configuration.

Read address ID can be 1 to 16 bits wide.

Table 20: AXI4-Lite Write Channel Interface Signals (Cont’d)

Name Direction Description

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 117 118

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