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3 Porting a BSP to Custom Hardware
3.3 Finalizing Your BSP
77
3
The L2 cache initialization routine sysL2CacheInit( ) should be called from
sysHwInit( ). This routine must not enable the L2 cache when cache is enabled, as
this is done by sysL2CacheEnable( ) later in the boot process. If your reference BSP
calls sysL2cacheInit( ) from sysHwInit2( ), it should be considered a bug in the
BSP.
3.3.6 Boot ROMs
Boot ROMs use the VxWorks kernel. The main differences between the bootrom
image and the vxWorks image are:
■
The bootrom image uses target/config/all/bootConfig.c instead of
target/config/all/usrConfig.c. These files are very similar, so getting the boot
ROM working involves essentially the same the steps described previously for
the vxWorks image.
■
The bootrom image is compressed by default. It is decompressed and copied
into RAM in the bootInit.c file.
During cleanup, each variation of the bootrom configuration should be tested.
3.3.7 Providing Bus Interface Support
Bus configuration is often required before devices on the bus can be supported.
This section describes how to configure several bus types—PCI, VME, USB—to
allow devices to be supported.
After the bus is configured, the devices on the bus can be configured.
PCI Bus Interface Support
The libraries pciConfigLib.c, pciConfigShow.c, pciIntLib.c, and pciAutoCfg.c
provide support for the PCI Bus Specification 2.1. These libraries support basic and
automatic configuration.
The PCI bus can be configured manually or automatically. Each method requires a
sysBusPci.c file to provide the BSP-specific routines for PCI configuration. To
configure PCI automatically, sysLib.c includes the following three files:
pciAutoConfigLib.c and pciConfigLib.c (located in the target/src/drv/pci
directory), and sysBusPci.c (located in the BSP directory). sysLib.c also includes a
- BSP DEVELOPER’S GUIDE 1
- U.S.): (800) 545-WIND 2
- Contents 3
- Contents 5
- Introduction 9
- BSP Developer’s Guide, 6.0 10
- 1.3 BSP Development Process 11
- 1.4 Terminology 12
- Overview of a BSP 13
- 2.2 Boot Sequence 15
- 2.2.1 Sequence Overview 16
- 2 Overview of a BSP 17
- Step 1: Execute romInit( ) 23
- Step 4: Execute usrInit( ) 25
- TCB) from the top 27
- 2.3 Components of a BSP 28
- USRCONFIG = usrConfig.c 29
- 2.3.2 Derived Files 36
- 2.3.4 Required Routines 40
- /* lock interrupts */ 46
- 2.3.5 Required Macros 47
- ROM_TEXT_ADRS. The offset 48
- 2.3.6 Optional Routines 50
- 2.4.1 BSP Debugging Methods 52
- 2.4.3 The Wind River IDE 56
- 2.4.5 Download Path 57
- 2.5 Avoiding Common Problems 61
- Porting a BSP to 63
- Custom Hardware 63
- 3.2.1 Initializing the Board 64
- 3.2.2 Initializing Memory 65
- LED Routines 70
- #undef INCLUDE_WDB_VIO 75
- 3.2.7 Interrupt Controllers 78
- 3.2.8 ISR Guidelines 78
- 3.2.9 DMA 78
- 3.2.11 Serial Drivers 79
- 3.3.2 Projects 81
- 3.3.3 Adding Other Timers 81
- 3.3.4 NVRAM 82
- 3.3.6 Boot ROMs 85
- FUNCPTR * pArg 89
- UINT * pArg 89
- 3.3 Finalizing Your BSP 101
- Generic Driver Introduction 110
- One-Shot Timer Examples 116
- Non-Volatile Memory 117
- Debugging Your BSP 123
- 4 Debugging Your BSP 127
- 4.2.3 Verifying RAM 129
- For example: 133
- 4.3.1 Symbols 134
- 4.3.2 Breakpoints 134
- Common Development Issues 139
- Image Locations 140
- A.3 Cache and MMU 141
- Timing Issues 142
- A.4 Reusing Unportable Code 143
- A.5 Volatile Variables 143
- Documentation Guidelines 145
- B.1 Introduction 146
- B.2 Written Style 146
- Use... Not 147
- B Documentation Guidelines 149
- Acronyms 152
- Board Names 153
- NAME Section 154
- B.4 Sections for target.ref 161
- B.5 Format and Style 163
- Ta b le B -5 Apigen Markup 166
- Component Input Output 170
- Command Syntax 174
- Board Diagrams 174
- B.6 Directives 175
- Directive Name Usage 176
- \IMAGE images/board.jpg 178
- \IMAGE images/switches.gif 178
- (apigen or refgen -mg) 182
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