
A Common Development Issues
A.3 Cache and MMU
133
A
If your system becomes unresponsive, verify that the RAM addresses the code is
actually loaded at match the addresses used in the code.
Position-Independent Code
One exception to the matching RAM addresses rule is the PIC instructions at the
beginning of the flash image.
In VxWorks, there is a short section of PIC that copies the image from flash to RAM
and then transfers execution to the copy in RAM. This includes the romInit( ) and
romStart( ) routines discussed in 2.2.4 Detailed Boot Sequence, p.15. The OS image
code must be linked to reside at the RAM address. However, when the image code
is programmed into flash, the addresses are different.
When verifying the addresses of the code in flash, the romInit( ) address must
match the address of the processor's reset vector. This does not match the address
in the bootrom image file.
A.3 Cache and MMU
A BSP that is running correctly without cache often encounters problems when
cache is enabled for the first time. In most cases, these problems are not the result
of problems with the cache library.
When accessing device registers or other shared memory, the processor should
invalidate the cache line before reading from the register, and it should flush the
cache line immediately after writing to the register. Failure to perform these steps
in the appropriate places in a driver or BSP can cause cache coherency problems.
When reading from a device register, the main processor may find the register data
in cache. In this case, it does not actually check the hardware unless the cache line
has been invalidated. Therefore, the value being read may no longer be valid.
When writing to a device register, the main processor puts information into a cache
line, but does not write it to RAM. Meanwhile, before the processor writes the
cached information to RAM, some other device can modify the memory that the
NOTE: In this discussion, the terms device register and register may refer to the
actual registers on some peripheral device or, they may refer to structures in RAM
that are manipulated by both the processor and the device.
Comentarios a estos manuales