RAM 6.0 BUX II Series Guía de usuario descargar pdf (Pagina 23)

2 Overview of a BSP

2.2 Boot Sequence

The MIPS processor uses a ModeIn input pin to set 256 bits of initialization

information. This information is stored in non-volatile memory, usually

somewhere other than on the processor chip. Board designers have the option of

providing this information in a special part of ROM or NVRAM dedicated to this

purpose. However, they might also design the board to gate this information from

the boot flash. If this is the case, the flash image must reserve 32 bytes at the

beginning of the image, initialized as required by the CPU.

The Intel i960 processor has a similar requirement called the initial boot record

(IBR). However, for the i960, instead of just 256 configuration bits, the IBR contains

an exhaustive table that defines memory regions, interrupt table information,

exception handling information, and other items. This IBR must be at a fixed

location, in much the way that the initial Program Counter is set to a fixed location

on other processors, and the BSP must know how to handle this situation.

The most common memory configuration is for RAM to be located at addresses

beginning with 0, and for flash to be addressed in regions of upper memory.

However, on some architectures and for some types of applications, it is customary

to design the board so that flash is located at address 0 and RAM is in upper

memory. In addition, many processors locate their interrupt vectors at address 0 by

default. For boards designed in such a way that the interrupt vectors are located in

flash, there are two requirements. First, a set of default interrupt vectors must be

located at the beginning of the flash image. Second, some mechanism must be

made available for the BSP to change the contents of the vectors when VxWorks

boots.

Some processors allow both big- and little-endian configurations. Typically, a BSP

supports only one byte order type. If both configurations are supported, a second

BSP is typically created and named with _le or _be suffix. For example, the

ixp1200eb BSP is configured for little-endian mode and the ixp1200eb_be BSP is

configured for big-endian mode. In this situation, the boot ROMs cannot typically

boot images from the other byte order.

2.2.4 Detailed Boot Sequence

The following is a step-by-step description of a generic boot sequence.

Step 1: Execute romInit( )

At power-up (cold start), the processor begins execution at the romInit( ) entry

point, located in romInit.s. For resets (warm starts), the processor begins execution

at romInit( ) plus a small offset (see sysToMonitor( ) in target/config/sysLib.c).

The romInit( ) routine must be written in assembly language.

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 188 189

Sin comentarios

RAM 6.0 BUX II Series Guía de usuario Pagina 23