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VxWorks

Hardware Considerations Guide, 6.0

4. Architecture Considerations

At the core of any VxWorks run-time environment is the target architecture. This

section is dedicated to the capabilities and run-time ramifications of architecture

selection. Some general observations follow, but most details are covered in

documents devoted to a particular architecture, the architecture supplements.

For additional documentation that pertains to VxWorks architecture support, refer

to the following:

■

VxWorks Architecture Supplement (for the appropriate target architecture)

■

VxWorks BSP Developer’s Guide

■

VxWorks Device Driver Developer’s Guide

■

Specific BSP Documentation (for a BSP closely related to your target)

■

Tornado User’s Guide (for VxWorks 5.x users)

■

Wind River Workbench User’s Guide (for VxWorks 6.0 users)

■

Wind River Technical Notes, available online through the Wind River Online

Support Web site

Interrupt Handling

Interrupts asynchronously connect the external world to the system, and are

typically the most important aspect of real-time systems. VxWorks adopts a

vectored interrupt strategy where applications “connect” ISRs (Interrupt Service

Routines) to a unique vector generated by the interrupting component. VxWorks

provides functions to dynamically program these vectors to contain the address of

an extremely small and fast code stub that calls an application’s C-language ISR,

and then returns control to the kernel.

A frustrating complication to ordinary interrupt servicing is interrupt

acknowledgment (IACK). Most system architectures provide for automatic

interrupt acknowledgment. For the relatively few that do not address this issue,

ISRs must manually acknowledge an interrupt through a register access or by

some other awkward mechanism.

Finally, interrupt latency may vary from architecture to architecture. Interrupt

latency is the maximum amount of time from the initial processor interrupt request

to the start of interrupt service processing. Both hardware and software contribute

to interrupt latency. The hardware may prioritize external interrupts, thereby

introducing an intrinsic latency to lower-priority interrupts.

Architectures often have indivisible instructions whose execution times are

surprisingly long. Especially problematic are cache push operations, which may

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