RAM 4.5 BUX II Series Manual de usuario descargar pdf (Pagina 9)

DE1 User Manual

• 512-Kbyte Static RAM memory chip

• Organized as 256K x 16 bits

• Accessible as memory for the Nios II processor and by the DE1 Control Panel

SDRAM

• 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip

• Organized as 1M x 16 bits x 4 banks

• Accessible as memory for the Nios II processor and by the DE1 Control Panel

Flash memory

• 4-Mbyte NOR Flash memory.

• 8-bit data bus

• Accessible as memory for the Nios II processor and by the DE1 Control Panel

SD card socket

• Provides SPI mode for SD Card access

• Accessible as memory for the Nios II processor with the DE1 SD Card Driver

Pushbutton switches

• 4 pushbutton switches

• Debounced by a Schmitt trigger circuit

• Normally high; generates one active-low pulse when the switch is pressed

Toggle switches

• 10 toggle switches for user inputs

• A switch causes logic 0 when in the DOWN (closest to the edge of the DE1 board) position

and logic 1 when in the UP position

Clock inputs

• 50-MHz oscillator

• 27-MHz oscillator

• 24-MHz oscillator

• SMA external clock input

Audio CODEC

• Wolfson WM8731 24-bit sigma-delta audio CODEC

• Line-level input, line-level output, and microphone input jacks

• Sampling frequency: 8 to 96 KHz

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RAM 4.5 BUX II Series Manual de usuario Pagina 9