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Silicon Updates

SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 15

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Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .

Advisory 6 DMA Access to L2 SRAM May Stall When the DMA and the CPU

Command Priority is Equal

Revision(s) Affected: 1.3, 1.2, 1.1, 1.0

Details: The L2 memory controller in the C64x+ Megamodule has programmable bandwidth

management features that are used to control bandwidth allocation for all requestors.

There are two parameters to control this feature: command priority and arbitration

counter MAXWAIT values.

Each requestor has a command priority and the requestor with the higher priority wins.

However, there are also counters associated with each requestor that track the number

of cycles each requestor loses arbitration. When this counter reaches a threshold

(MAXWAIT), which is programmed by the user (or default value), the losing requestor

gets an arbitration slot and wins for that cycle.

There are four such requestors: CPU, DMA (SDMA and IDMA), user cache coherency

operation, and global cache coherence. Global-coherence operations are highest

priority, while user-coherence operations are lowest priority. However, there is active

arbitration done for the CPU and the DMA (SDMA/IDMA) commands. The priority

for DMA commands comes from an external master as part of the SDMA command or

a programmable register, IDMA1_COUNT, in the C64x+ Megamodule for IDMA

commands. The priority for CPU accesses to L2 is in a programmable register,

CPUARBU, in the C64x+ Megamodule. For the default priority values, see Table 5.

The L2 memory controller is supposed to give equal bandwidth to the DMA and the

CPU, by alternating between the two for arbitration. Instead, the L2 memory controller

gives larger bandwidth allocation to the CPU accesses when the DMA and the CPU

priorities are the same. The CPU commands keep winning arbitration over the DMA

as long as there are no other internal conditions (stalls, etc.) that force the DMA to win

arbitration. This typically happens when CPU accesses keep the L2 memory controller

Table 5 C6457 Default Master Priorities

Master

Default Master Priorities

0 = Highest Priority

7 = Lowest Priority

Priority Control

EDMA3TCx 0 QUEPRI.PRIQx

(EDMA3 Register)

1. EDMA3 Register

SRIO (Data Access) 0 PER_SET_CNTL.CBA_TRANS_PRI

2. SRIO Register

SRIO (Descriptor Access) 1 PRI_ALLOC.SRIO_CPPI

EMAC 1 PRI_ALLOC.EMAC

HPI 2 PRI_ALLOC.HOST

End of Table 5

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