PPP and ATM Termination Type C RAM Package Release 1.4.1
6 Freescale Semiconductor
Table 8. Revision History—Revision 1.1.0
Release 1.1.0
New Features
High-speed SS7 links support.
Support for ITU-T Q.703 Annex A, Chinese National SS7 YDT 1125-2001.
Bug Fixes
In the 1588V2, the Timestamp is presented in little-endian instead of big endian.
ML/MC PPP receiver has a synchronization flaw between the front-end and back-end processes that can
cause the loss of received ML fragments.
When working in Fast Ethernet Half Duplex and a collision error occurs the port might halt .
In an Ethernet Rx in heavy traffic (when smoother is disabled) load or in case of an errored frame (CRC,
IP Check Sum etc..) and the frame size is less than 128 bytes unexpected behavior may occur.
Ethernet receiver can cause unpredictable memory corruption while discarding illegal short frames.
Working with customized preamble is not supported for frames smaller then 64 bytes.
In ATM GCRA scheduler, in the case that there is no Channel Code under one of the GCRA priority levels
there is a possibility of wrong ATM traffic shaping.
When the Ethernet receive is highly loaded with in coming frames it might stop functioning at all.
This bug is valid only if the next two conditions take place:
1. More than one threads are enabled.
2. The maximum length of the incoming frames is longer than 4 × (VFIFO block size). (VFIFO block size
= 128 up to 248). QENET22
Table 9. Revision History—Revision 1.0.0
Release 1.0.0
New Features
ESS7 functionality was added.
The content of the package was changed. Ethernet to Ethernet interworking was removed.
Bug Fixes
When working with Ethernet, the LossLess flow control feature can be enabled by mistake and the
transmitter may send a flow control frame.
Table 10. Revision History—Revision 0.1.1
Release 0.1.1
New Features
ML PPP—Adaptive Sequence Number Mechanism. This feature allows the microcode to synchronize on
ML traffic in case of a temporary outage on the lines. In case of successful synchronization a special
interrupt will be issued. This interrupt can be disabled by setting BMR[DisAdSeqInt] on BPT.
Bug Fixes
In PPP termination, if the interrupt bit in the TxBD is asserted it might cause memory corruption.
A dynamic change of Ethernet Tx Rate limiter might cause the Ethernet Tx to halt.
Errata of QENET 20 was fixed. In order for it to run properly the TEMODER[6] in the Tx Ethernet global
parameter RAM has to be set for the Fast Ethernet Half Duplex UCC and the Tx RMONs have to be
enabled and UPSMR[7] bit has to be set.
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